3D Memory Source Layer Segmentation for Reliable Coupling
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Solution Overview
Problem
As the number of stacked memory cells in three-dimensional semiconductor memory devices increases, it becomes difficult to reliably couple the channel layer with the source layer, affecting the electrical characteristics of the source layer.
Innovation Solution
A semiconductor device is designed with a first and second source seed layer, cell plugs, and an interlayer source layer, where a dummy plug penetrates through the second source seed layer and extends into the first source seed layer to stabilize the source area, ensuring reliable electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked memory cells is increased to achieve high integration, then the storage capacity is improved, but the difficulty in coupling the channel layer with the source layer increases and electrical characteristics of the source layer deteriorate
Solution Approach 1:
The source layer is segmented into multiple parts: first source seed layer, second source seed layer, and interlayer source layer. This segmentation allows each layer to perform specific functions - the seed layers provide growth nuclei while the interlayer source layer ensures reliable electrical coupling, thereby maintaining source layer electrical characteristics even as memory cell stacking increases
Solution Approach 2:
The patent transitions from a planar source layer configuration to a three-dimensional multi-layer source structure. By adding the interlayer source layer between the first and second source seed layers, the solution addresses the coupling difficulty in the vertical dimension, enabling reliable electrical characteristics to be maintained as the device scales to higher integration with increased memory cell stacking
2Productivity
If the number of stacked memory cells is increased, then the integration density is improved, but the difficulty in securing reliable electrical characteristics of the source layer increases
Solution Approach 1:
The source layer is divided into multiple functional segments (first source seed layer, second source seed layer, interlayer source layer) that work together to maintain electrical characteristics. This segmentation enables the structure to achieve high integration density while preserving reliable electrical performance through dedicated coupling functions in each layer
Solution Approach 2:
The interlayer source layer acts as an intermediary between the first and second source seed layers, facilitating reliable electrical coupling. This intermediate layer ensures that as integration density increases with more stacked memory cells, the electrical characteristics of the source layer remain secure through the mediating coupling function
Data Source
AI summary
Provided here may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a first source seed layer, a second source seed layer disposed over the first source seed layer at a position spaced apart from the first source seed layer with a source area interposed between the first source seed layer and the second source seed layer, cell plugs configured to penetrate through the second source seed layer and extend into the source area, the cell plugs being disposed at positions spaced apart from the first source seed layer. The semiconductor device may also include an interlayer source layer configured to fill the source area.