Programmable Logic Block Control for Clock Skew Balancing

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Solution Overview

Problem

Programmable logic circuits face operational defects due to clock skew caused by transistor degradation over time, which existing low-power consumption techniques fail to address effectively.

Innovation Solution

A logic block control system that determines and equalizes the operation times of logic blocks to prevent degradation, using a determination unit to identify blocks for stopping and a control unit to adjust their connection states, employing gated clock and power-off techniques to minimize power consumption and reduce clock skew.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If low-power consumption techniques (gated clock and power-off) are applied to stop operations of logic blocks, then power consumption is reduced, but clock skew occurs due to unequal operation times of logic blocks

Engineering Contradiction:
Improvepower consumptionVSAvoiddata transfer correctness
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent implements dynamic operation time management by continuously monitoring the cumulative operation time of each logic block and dynamically adjusting which blocks are stopped or kept running based on current low-power modes. This dynamic approach allows the system to adaptively balance power consumption reduction with maintaining acceptable clock skew levels, preventing data transfer errors while maximizing energy savings.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters by tracking cumulative operation times of individual logic blocks and using these parameters to make informed decisions about which blocks to stop. By monitoring operation time as a key parameter and adjusting stop decisions accordingly, the system prevents excessive clock skew accumulation while maintaining low power consumption during idle periods.

Inventive Principle:
Principle #35Parameter changes

2Loss of energy

If logic blocks are stopped to reduce power consumption, then energy savings are achieved, but degradation levels become unequal across logic blocks causing operational defects

Engineering Contradiction:
Improvepower consumption reductionVSAvoiddegradation level uniformity
Core Design Contradiction:
Loss of energyVSStability of the object's composition

Solution Approach 1:

The patent implements a feedback mechanism that continuously monitors the cumulative operation time of each logic block and uses this information to make intelligent stop decisions. By feeding back operation time data to the control logic, the system can identify which blocks have accumulated sufficient operation time and are safe to stop, thereby maintaining uniform degradation levels across all blocks while achieving power consumption reduction.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

Each logic block's operation time is self-tracked and recorded, allowing the system to make autonomous decisions about which blocks to stop based on their individual usage patterns. This self-service approach enables the system to automatically balance degradation across blocks without requiring external intervention or complex centralized control.

Inventive Principle:
Principle #25Self-service

3Reliability

If all logic blocks operate continuously, then data transfer correctness is maintained, but power consumption increases

Engineering Contradiction:
Improvedata transfer correctnessVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies partial action by stopping only those logic blocks that have accumulated sufficient operation time and are therefore safe to halt, rather than stopping all blocks uniformly. This selective approach allows the system to reduce power consumption by idleing appropriate blocks while maintaining continuous operation of blocks that are currently needed for correct data transfer, achieving energy savings without compromising reliability.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS7579864B2Logic block control system and logic block control method
Publication Date: 2009.08.25 PANASONIC HOLDINGS CORP
  • US7579864B2 patent drawing
  • US7579864B2 patent drawing
  • US7579864B2 patent drawing

AI summary

The number of blocks that can be stopped when performing target processing in a programmable logic unit is obtained, and a stop rate of each of a plurality of logic blocks included in the programmable logic unit is calculated. The same number of logic blocks as the blocks that can be stopped are selected from among the plurality of logic blocks in ascending order of a stop rate, the selected logic blocks are determined as logic blocks whose operations are to be stopped, and the operations are stopped. As a technique of stopping an operation of a logic block, a gated clock technique, a power-off technique, or the like is used.