APD Pixel Wiring Layout for Stable Current Supply and Photon Counting
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Solution Overview
Problem
The high wiring density in avalanche photodiode (APD) sensors leads to issues with stable current supply and efficient photon counting, particularly at high luminance, due to the complexity and density of power supply wiring.
Innovation Solution
A novel wiring configuration is introduced where multiple wiring layers are stacked between semiconductor layers, allowing for a two-dimensional layout of power supply wiring to intersect both ends of pixel circuits in both directions, ensuring stable current supply and efficient photon counting by reducing wiring resistance and increasing the occupation area of power supply wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high wiring density is used in APD sensor to supply power to pixel circuits, then power supply capability is improved, but wiring resistance increases and current supply stability deteriorates
Solution Approach 1:
The patent transitions from conventional planar wiring layout to a three-dimensional stacked wiring architecture. Multiple wiring layers are arranged vertically between the first substrate and second substrate, allowing power supply wiring to extend in the thickness direction (z-axis) while also covering horizontal directions (x-y plane). This dimensional expansion enables sufficient power delivery capability without requiring excessive wiring density in any single plane, thereby maintaining current supply stability even at high luminance conditions.
Solution Approach 2:
The power supply wiring is divided into multiple segments across different wiring layers. Each wiring layer contains specific power supply lines that collectively form a comprehensive power distribution network. This segmentation allows current to be supplied through multiple parallel paths, reducing the burden on individual wiring segments and preventing overheating or voltage drops that would compromise stability.
2Reliability
If wiring layer occupation area is increased to reduce wiring resistance, then current supply stability is improved, but device area is increased
Solution Approach 1:
Instead of expanding wiring occupation area within a single plane, the patent utilizes the thickness direction by stacking multiple wiring layers. This vertical arrangement allows the total wiring cross-sectional area to be distributed across multiple layers, effectively reducing wiring resistance without increasing the planar footprint of the device. The three-dimensional wiring structure achieves superior current supply stability while maintaining a compact device profile.
Solution Approach 2:
Multiple wiring layers are nested vertically within the device structure, with each layer containing power supply wiring that complements the layers above and below. This nested arrangement maximizes the use of available space in the thickness direction, allowing sufficient wiring cross-sectional area for low resistance while keeping the overall device area minimal.
3Productivity
If complex wiring configuration is implemented to manage high wiring density, then power supply efficiency is improved, but device complexity is increased
Solution Approach 1:
The patent simplifies the wiring configuration by exploiting the third dimension. Rather than implementing complex routing patterns within planar layers to manage high wiring density, the solution stacks multiple wiring layers vertically, allowing straightforward power distribution through the thickness direction. This approach achieves high power supply efficiency with relatively simple wiring patterns in each layer, as the vertical stacking naturally provides multiple parallel current paths without requiring elaborate in-plane routing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables stable current supply to pixel circuits, even at high luminance, by effectively managing the high wiring density and ensuring efficient photon counting, thereby improving the performance of APD sensors.
Implementation Method 1
In each pixel, a reverse bias voltage is applied to the PN junction diode, whereby a photocharge resulting from a single photon causes avalanche multiplication.
Implementation Method 2
a photocharge resulting from a single photon causes avalanche multiplication
Data Source
AI summary
The wiring is configured so that both ends of a region including each of a plurality of pixel circuits in a first direction and both ends of the region in a second direction intersecting the first direction are connected by a combination of a wiring layer group.