Thin Film Transistor Offset Elimination via Asymmetric Gate Insulator
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Solution Overview
Problem
Conventional top gate type thin film transistors suffer from offset regions that increase the on/off current ratio and decrease current during the 'on' period, and contact resistance issues at the active layer and electrode contact regions.
Innovation Solution
A thin film transistor design featuring a silicone-based organic gate insulating layer with a specific inverted trapezoidal shape and a structure that eliminates offset regions, using a first and second metal sub-layer to reduce contact resistance, and a fabrication method that aligns electrode and channel regions for improved electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional top gate type thin film transistor structure is used, then the device can be manufactured with standard processes, but offset regions are formed that increase on/off current ratio and decrease current during on period
Solution Approach 1:
The patent removes the offset regions entirely by aligning the gate electrode edges with the active layer edges. This extraction of the problematic offset regions eliminates the harmful effects of increased on/off current ratio and decreased on-period current, while maintaining standard manufacturing processes.
Solution Approach 2:
The patent introduces asymmetry in the gate insulating layer thickness, making it thicker at the source and drain contact regions compared to the channel region. This asymmetric thickness distribution improves contact characteristics and reduces contact resistance without affecting the overall device manufacturability.
2Ease of manufacture
If conventional top gate type thin film transistor structure is used, then the fabrication process is straightforward, but contact resistance at active layer and electrode contact regions is increased
Solution Approach 1:
The gate insulating layer is designed with asymmetric thickness: thicker portions at the source and drain contact regions and a thinner portion over the channel region. This asymmetric structure improves electrical contact characteristics and reduces contact resistance while maintaining fabrication simplicity through standard coating and etching processes.
Solution Approach 2:
The patent applies local quality by varying the gate insulating layer thickness at different locations: thicker regions at contact points for better electrical contact and thinner regions over the channel for optimal transistor operation. This localized variation addresses contact resistance issues without complicating the overall fabrication process.
3Ease of manufacture
If offset regions are present in the transistor structure, then the gate electrode can be easily formed, but the on/off current ratio increases and current during on period decreases
Solution Approach 1:
The patent extracts and eliminates the offset regions by designing the gate electrode to have edges that substantially align with the active layer edges. This removal of offset regions directly addresses the current characteristics problem while gate electrode formation remains straightforward through standard photolithography and etching processes.
Data Source
AI summary
The present application discloses a thin film transistor including a base substrate; an active layer on the base substrate comprising a channel region, a source electrode contact region, and a drain electrode contact region; a gate insulating layer on a side of the channel region distal to the base substrate; and a gate electrode on a side of the gate insulating layer distal to the channel region; the gate insulating layer being made of a silicone-based organic material.