Stacked TFT Display Structure for Aperture and Driving Stability
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Solution Overview
Problem
As the resolution of display apparatuses and the number of thin film transistors (TFTs) connected to a single display device increase, the pixel aperture ratio decreases, leading to inefficiencies in display performance.
Innovation Solution
A display apparatus is designed with a first and second TFT disposed on different layers, where the second TFT has a thinner active layer and a conductive layer is placed between them, functioning as a shielding layer to prevent coupling and stabilize the driving of the second TFT, while a planarization layer ensures a flat surface for improved coverage and reduced influence from lower wiring patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of display apparatuses and the number of TFTs connected to a single display device are increased, then the display resolution is improved, but the pixel aperture ratio decreases
Solution Approach 1:
The patent transitions from a planar arrangement of TFTs to a three-dimensional stacked configuration where TFTs are disposed on different layers (first layer and second layer). This vertical stacking enables multiple TFTs to occupy the same horizontal pixel area, thereby increasing the number of TFTs per pixel without further reducing the pixel aperture ratio on the display surface.
Solution Approach 2:
The patent implements a nested structure where the second TFT is positioned on top of the first TFT within the same pixel region. The second TFT's active layer is disposed on the first TFT's structure, creating a hierarchical arrangement that maximizes space utilization and maintains pixel aperture while accommodating multiple transistors.
2Area of stationary object
If multiple TFTs are disposed on different layers, then the pixel aperture ratio is maintained, but coupling between TFTs occurs causing instability in driving
Solution Approach 1:
The patent introduces a conductive layer positioned between the first TFT and the second TFT, specifically between their active layers. This conductive layer acts as a shielding intermediary that prevents harmful electrical coupling and interference between the stacked TFTs, thereby stabilizing the driving of the second TFT while maintaining the vertical stacked configuration.
Solution Approach 2:
The conductive layer is pre-positioned between the TFTs to preemptively block coupling effects before they can occur. By placing this shielding layer in advance during the stacking process, the patent prevents instability issues from arising in the first place, rather than attempting to correct them afterward.
3Reliability
If a conductive layer is added between TFTs, then coupling is prevented and driving stability is improved, but the device complexity increases
Solution Approach 1:
The conductive layer serves multiple functions simultaneously: it acts as a shielding layer to prevent coupling between TFTs, provides electrical connection functionality, and contributes to the overall structural integrity of the stacked configuration. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity.
4Volume of moving object
If the second TFT has a thinner active layer, then the stacking configuration is enabled, but manufacturing precision requirements increase
Solution Approach 1:
The patent modifies the thickness parameter of the second TFT's active layer, making it thinner than conventional designs. This parameter change enables the vertical stacking configuration by reducing the height of the second TFT, allowing it to be positioned on top of the first TFT within the available space while maintaining proper electrical characteristics.
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A
AI summary
A display apparatus including a first thin film transistor disposed on a substrate and including a first active layer, a second thin film transistor disposed on the first thin film transistor and including a second active layer overlapping the first thin film transistor, a first planarization layer disposed between the first thin film transistor and the second thin film transistor, the first planarization layer including a first insulating layer and a second insulating layer disposed on the first insulating layer, and a first buffer layer disposed between the first planarization layer and the second thin film transistor, in which an upper surface of the second insulating layer and an upper surface of the first insulating layer are substantially flush with each other.