Dual Metal Layer Bit Line Structure for Non-Volatile Memory
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Solution Overview
Problem
In non-volatile memory systems, capacitive coupling between bit lines leads to read errors due to increased bit line capacitance and parasitic capacitance, which worsens with transistor scaling, necessitating time-consuming sequential sensing of odd or even bit lines to mitigate crosstalk.
Innovation Solution
Forming bit lines in two separate metal layers at a 4f pitch with alternating arrangements and incorporating grounding shields between bit lines in each layer to reduce capacitance and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bit lines are formed in a single metal layer at 2f pitch, then device density is improved, but capacitive coupling between bit lines increases causing read errors
Solution Approach 1:
The patent transitions from a single-layer bit line configuration to a dual-layer configuration, where bit lines are distributed across two separate metal layers. This dimensional change in the vertical direction (adding a Z-axis layer dimension) allows bit lines to be spaced farther apart while maintaining the same planar density, thereby reducing parasitic capacitance and crosstalk between adjacent bit lines.
Solution Approach 2:
The bit line system is segmented into two separate metal layers, with each layer containing a subset of bit lines. This segmentation divides the originally dense single-layer bit line array into two less-dense layers, reducing the capacitive coupling between neighboring bit lines while maintaining overall connectivity and functionality.
2Measurement precision
If sequential sensing of odd or even bit lines is performed to reduce crosstalk, then read accuracy is improved, but sensing time increases
Solution Approach 1:
By distributing bit lines across two vertical layers, the patent enables parallel sensing of all bit lines simultaneously without excessive crosstalk. This eliminates the need for sequential odd-even sensing schemes, as the physical separation in the vertical dimension provides sufficient isolation for accurate parallel read operations.
3Quantity of substance
If transistor scaling is continued to increase density, then device capacity is improved, but parasitic bit line capacitance increases
Solution Approach 1:
The patent addresses the parasitic capacitance issue arising from transistor scaling by moving bit lines into a third dimension (vertical layering). This allows continued miniaturization and increased device density in the planar direction while maintaining larger spacing between bit lines through vertical separation, thereby controlling parasitic capacitance despite continued scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces bit line to bit line capacitance, improving sensing speed and memory performance by minimizing crosstalk effects, allowing for faster and more accurate data retrieval with reduced energy consumption.
Implementation Method 1
capacitance is reduced and performance is improved
Implementation Method 2
incorporating grounding shields between bit lines in each layer to reduce capacitance and enhance performance
Data Source
AI summary
Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4f pitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer.