5T SRAM Cell With Mid-Level Precharge for Faster Sensing
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Solution Overview
Problem
The semiconductor industry seeks alternatives to traditional 6-transistor static random access memory (SRAM) designs to achieve smaller memory cell sizes and faster performance, as larger caches reduce off-chip memory access but require more efficient memory cell configurations.
Innovation Solution
A 5-transistor SRAM memory cell design is implemented, featuring a P-type pass gate transistor and a pre-charge circuit with an n-type transistor, which allows for natural pre-charge voltage levels without additional circuitry, and uses a second bit line as a reference for the sense amplifier, enabling faster sensing and lower signal-to-noise ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional 6-transistor SRAM design is used, then reliability is maintained, but memory cell size is larger
Solution Approach 1:
The patent extracts one transistor from the traditional 6-transistor SRAM configuration, removing the need for a dedicated write transistor by utilizing the pass gate transistor's bidirectional conduction capability. This reduction from 6T to 5T directly decreases the memory cell area while maintaining functionality through the inherent properties of the pass gate transistor structure.
Solution Approach 2:
The pass gate transistor serves multiple functions simultaneously: it acts as both the write transistor and the access transistor for read operations. This multi-functionality is achieved by configuring the pass gate transistor to conduct bidirectionally, allowing it to perform write operations when needed and serve as the access transistor during read operations, thereby eliminating the need for a separate write transistor.
2Productivity
If cache size is increased to store more recent data, then off-chip memory access is reduced, but memory cell density decreases
Solution Approach 1:
The patent changes the fundamental parameter of transistor count from 6 to 5 per memory cell, which directly reduces the area occupied by each memory cell. This parameter change enables higher memory cell density, allowing larger cache sizes to be implemented within the same chip area, thereby improving off-chip memory access efficiency by providing more on-chip storage capacity.
3Area of moving object
If 5-transistor SRAM design is implemented, then memory cell size is reduced, but additional pre-charge circuitry is required
Solution Approach 1:
The patent merges the pre-charge function with the bit line structure itself, using the bit line as both the data transmission path and the pre-charge path. The bit line is pre-charged to a specific voltage level (VBL) through dedicated pre-charge transistors, eliminating the need for separate pre-charge circuitry and reducing overall device complexity while maintaining the 5T configuration.
Solution Approach 2:
The patent introduces a reference bit line that serves as an intermediary element for the sense amplifier operation. This reference bit line is pre-charged to a specific voltage and provides a reference level against which the differential signal from the memory cell is measured, enabling the sense amplifier to detect stored data without requiring additional complex pre-charge mechanisms.
4Speed
If second bit line is used as reference for sense amplifier, then sensing speed is improved, but signal-to-noise ratio decreases
Solution Approach 1:
The patent changes the voltage parameter of the bit lines by pre-charging them to a specific intermediate voltage level (VBL) rather than using full rail-to-rail swings. This voltage parameter adjustment allows for faster sensing by reducing the time constant of the RC circuit formed by the bit line capacitance and resistance, while the reference bit line configuration maintains adequate signal-to-noise ratio through differential sensing.
Data Source
AI summary
A memory circuit includes a first and a second bit line, a first memory cell, a first P-type pass gate transistor, a pre-charge circuit, a first transmission gate and a sense amplifier. The first memory cell includes a first storage node coupled to the second bit line, and a second storage node not coupled to any bit line. The first P-type pass gate transistor is coupled between the first storage node and the second bit line. The pre-charge circuit is configured to charge the first or second bit line to a pre-charge voltage responsive to a first signal. The pre-charge voltage is between a voltage of a first and a second logical level. The first transmission gate is coupled to the second bit line, and configured to receive a first and second control signal. The sense amplifier is coupled to the second bit line by the first transmission gate.