Stilted Pad Structure for BSI Bondability and Lower Delamination
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge with existing methods for forming pad structures in backside illuminated (BSI) image sensors is poor bondability due to a small bond area and high backside topography variation, which increases processing costs and complexity, especially when dealing with variations in semiconductor substrate thickness.
Innovation Solution
A stilted pad structure is formed using a method that includes selective etches to create openings with a pad protrusion extending from the pad body to the wire, allowing for a larger bond area and reducing delamination risk, while omitting the need for a dielectric filler layer to simplify processing and reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional pad structure is used in BSI image sensors, then the manufacturing process is simpler, but the bondability is poor due to small bond area
Solution Approach 1:
The pad structure transitions from a conventional planar configuration to a three-dimensional stilted configuration with protrusions extending vertically. This dimensional change increases the bond area by creating multiple contact points (pad body and protrusions) that can bond to underlying wires, thereby improving bondability while maintaining manufacturing feasibility through selective etching processes
2Reliability
If the pad structure is inset deep into the backside to increase bond area, then bondability improves, but backside topography variation increases
Solution Approach 1:
The pad structure is segmented into multiple components: a pad body portion inset into the backside and multiple protrusions extending toward the frontside. This segmentation allows the bond area to be distributed across different vertical levels, improving bondability while the protrusions reach upward to reduce the effective inset depth, thereby mitigating backside topography variation
3Reliability
If selective etching is used to create the stilted pad structure, then bondability improves, but processing complexity increases
Solution Approach 1:
The pad structure is formed using preliminary selective etching steps that create the stilted configuration before final pad formation. By pre-establishing the three-dimensional protrusion structure through selective etching of trenches and deposition of conductive material, the subsequent pad formation process is simplified, and the enhanced bondability is achieved without requiring complex post-processing steps
4Manufacturing precision
If a dielectric filler layer is added to fill unfilled portions, then manufacturing precision improves, but processing costs increase
Solution Approach 1:
The invention extracts and eliminates the dielectric filler layer step from the conventional manufacturing process. By designing the pad structure with protrusions that extend upward to contact wires, the need for filling unfilled portions with dielectric material is removed. This simplification maintains manufacturing precision through the self-aligning nature of the selective etching process while reducing processing complexity and costs
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a stilted pad structure. A wire underlies a semiconductor substrate on a frontside of the semiconductor substrate. Further, a trench isolation structure extends into the frontside of the semiconductor substrate. The stilted pad structure is inset into a backside of the semiconductor substrate that is opposite the frontside. The stilted pad structure comprises a pad body and a pad protrusion. The pad protrusion underlies the pad body and protrudes from the pad body, through a portion of the semiconductor substrate and the trench isolation structure, towards the wire. The pad body overlies the portion of the semiconductor substrate and is separated from the trench isolation structure by the portion of the semiconductor substrate.


