PoP Semiconductor Package with Preformed Through Mold Vias
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices with package on package (PoP) structures face challenges in achieving high manufacturing accuracy and yield due to the complexity of forming through mold vias with external connection terminals, which requires intricate processes and can lead to mechanical strength issues and warpage.
Innovation Solution
The semiconductor device design involves forming through mold vias penetrating the molding material and protective film before bonding the die to the protective film, with a seed layer on the vias and external connection terminals connected to the lower end portions, allowing for a simpler manufacturing process and improved mechanical strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If through mold vias are formed after die bonding with external connection terminals, then mechanical strength is improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The through mold via is formed in advance on the protective film before die bonding, rather than after. This preliminary action simplifies the manufacturing process by eliminating the need for complex post-bonding via formation and external connection terminal mounting, while the via structure itself provides the necessary mechanical reinforcement.
2Volume of moving object
If substrate thickness is reduced for high integration, then integration density is improved, but mechanical strength and warpage control deteriorate
Solution Approach 1:
The protective film is designed with non-uniform thickness, being thicker at the peripheral regions and thinner at the center where the die is mounted. This local quality variation provides enhanced mechanical strength and warpage control at the edges while maintaining low profile and high integration density in the central active area.
Data Source
AI summary
A semiconductor device that can be manufactured with higher accuracy and higher yield without the need of a complicated process, a method for manufacturing a semiconductor device, and an electronic device including the semiconductor device are disclosed. A configuration includes: a first package including a die of an integrated circuit, a protective film on an upper surface of the die, the protective film being larger in area than the die, a first molding material covering an outer periphery of the die, a plurality of through mold vias penetrating the first molding material and the protective film, a seed layer on upper end portions and peripheral side surfaces of the through mold vias, and an external connection terminal connected to lower end portions of the through mold vias; and a second package on an upper surface of the protective film of the first package and connected to the upper end portions of the through mold vias.