Programmable CMOS Delay Cell With Uniform Footprint and Skew Tuning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In CMOS integrated circuits, achieving balanced rise and fall delays across various manufacturing processes, voltages, and temperatures is challenging due to the use of long-channel transistors, which leads to timing issues and potential circuit failure, especially when poly-gate Critical Dimension variations occur.
Innovation Solution
A programmable delay cell with configurable source-drain connections between stacked PMOS and NMOS transistors allows for adjustable delay values and skew settings, maintaining a uniform cell size and layout regardless of the delay or drive strength, enabling flexible tuning of rise and fall times without altering the physical size or terminal locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If long-channel transistors are used in delay cells, then delay tuning capability is improved, but manufacturing precision deteriorates due to poly-gate Critical Dimension variations
Solution Approach 1:
The patent changes the physical parameters of the transistors by using minimum channel length instead of long channel length, and by adjusting transistor width ratios to achieve delay tuning while maintaining manufacturing precision and reducing sensitivity to poly-gate Critical Dimension variations
Solution Approach 2:
The patent introduces configurable source-drain connections that allow dynamic reconfiguration of the transistor network to achieve different delay values and skew settings, enabling flexible delay tuning without relying on long-channel transistor geometry
2Adaptability or versatility
If delay cell delay values are adjusted by changing transistor channel length, then delay tuning is improved, but device complexity increases
Solution Approach 1:
The patent uses configurable source-drain connections that can be selectively activated or deactivated to dynamically adjust the effective delay of the cell without changing the physical transistor structure, thereby achieving delay tuning while maintaining simple device geometry
Solution Approach 2:
The same transistor network serves multiple functions: it provides delay adjustment, skew control, and maintains uniform cell footprint, eliminating the need for separate structures for each function and reducing overall device complexity
3Ease of manufacture
If uniform cell size is maintained across different delay values, then ease of manufacture is improved, but adaptability deteriorates
Solution Approach 1:
The patent achieves uniform cell footprint while maintaining adaptability by using configurable source-drain connections that can be programmed to provide different delay values and skew settings within the same physical structure, allowing the cell to adapt its electrical characteristics without changing its physical dimensions
Data Source
AI summary
Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.