3D Memory Stack With Bent Backside Word Lines for Dense Routing
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Solution Overview
Problem
As feature sizes of planar memory cells approach their limits, traditional fabrication techniques become challenging and costly, leading to density limitations in memory devices, which 3D memory architecture aims to address by increasing memory density and reducing interconnect complexity.
Innovation Solution
The method involves forming 3D memory devices with bent backside word lines by creating notches on the substrate, depositing semiconductor layers and alternating conductive and dielectric layers, and replacing sacrificial layers with conductive ones to create a memory stack that extends on both sides of the substrate, allowing for increased routing flexibility and memory cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but fabrication complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture. The memory stack structure extends vertically with alternating conductive and dielectric layers forming a 3D configuration, allowing memory density to increase without proportionally increasing fabrication complexity. The bent word lines extend from the front surface, wrap around the stack, and connect to the back surface, creating a 3D interconnect structure that reduces the number of separate contact formation processes needed.
2Quantity of substance
If traditional fabrication techniques are used for planar memory cells, then manufacturing simplicity is maintained, but memory density reaches an upper limit
Solution Approach 1:
The memory device is segmented into distinct functional regions: a memory stack portion extending vertically from the front surface, and peripheral devices formed on the back surface. The bent word lines create separate interconnect regions that route signals between the front and back surfaces. This segmentation allows independent optimization of memory array and peripheral circuit fabrication processes.
3Device complexity
If 3D memory architecture is implemented with bent backside word lines, then interconnect routing is simplified and chip area is reduced, but fabrication process complexity increases
Solution Approach 1:
The word lines are formed as bent structures that extend from the front surface, wrap around the memory stack, and connect to the back surface before peripheral devices are fully formed. This preliminary formation of the 3D interconnect structure simplifies subsequent routing operations and reduces the need for separate contact formation processes, as the bent word lines themselves serve as the interconnect pathway between front and back surfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory cell density, reduces chip area usage, and simplifies interconnect routing, while lowering costs and improving electrical performance by enabling word line contacts to be formed without separate contact formation processes.
Implementation Method 1
The sacrificial layers are replaced with a plurality of conductive layers
Implementation Method 2
A plurality of interleaved conductive layers and dielectric layers are formed along a front side and the at least one edge of the semiconductor layer and along a top surface, a side surface, and a bottom surface of the notch
Data Source
Figure 1A
Figure 1B
Figure 2A~2B
AI summary
A method for forming a 3D memory device is provided. A notch is formed on at least one edge of a substrate (302). A semiconductor layer above the substrate and extending laterally beyond the at least one edge of the substrate is formed to cover the notch (304). A plurality of interleaved conductive layers and dielectric layers are formed along a front side and the at least one edge of the semiconductor layer and along a top surface, a side surface, and a bottom surface of the notch (306). A portion of the substrate is removed to expose the interleaved conductive layers and dielectric layers below the semiconductor layer (308).