3D Embedded Non-Volatile Memory Stack for BEOL Thermal Compatibility
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Solution Overview
Problem
Embedded non-volatile memory is limited by two-dimensional design, restricting its capacity and compatibility with advanced semiconductor processes, particularly in terms of storage density and thermal compatibility during manufacturing.
Innovation Solution
A three-dimensional memory device is developed with stacks of memory cells formed by laterally separated stacking structures, including access and storage transistors connected via a common node, using conductive, isolation, and channel layers, along with gate and switching layers, allowing for increased storage density and reduced thermal damage during processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional design is used for embedded non-volatile memory, then manufacturing simplicity is maintained, but storage capacity is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory architecture to three-dimensional stacked memory architecture. Multiple memory cells are vertically stacked across multiple layers, with interlayer connections established through conductive layers. This vertical stacking enables significantly increased storage capacity without proportionally increasing the footprint area, directly resolving the contradiction between storage capacity and design dimensionality.
2Reliability
If conventional memory structures are used, then CMOS process compatibility is maintained, but thermal damage to BEOL structures occurs during programming
Solution Approach 1:
The patent employs metallic gate structures instead of conventional polysilicon gates. This parameter change in gate material enables lower programming voltages to be applied during memory programming operations. The reduced voltage requirement directly decreases thermal damage to BEOL structures while maintaining CMOS process compatibility, resolving the contradiction between reliability and harmful thermal effects.
3Quantity of substance
If three-dimensional stacked architecture is implemented, then storage density is increased, but manufacturing complexity increases
Solution Approach 1:
The patent divides the memory structure into multiple stacked layers, each containing memory cells with access transistors and storage transistors. Conductive layers are inserted between stacked memory cells to enable electrical connections. This segmentation approach allows modular fabrication and assembly, reducing overall manufacturing complexity despite the three-dimensional architecture, thereby resolving the contradiction between storage density and ease of manufacture.
Data Source
AI summary
A memory device, a semiconductor device and a manufacturing method of the memory device are provided. The memory device includes first, second and third stacking structures, first and second channel structures, a gate dielectric layer, a switching layer, and first and second gate structures. The first, second and third stacking structures are laterally spaced apart from one another, and respectively comprise a conductive layer, an isolation layer and a channel layer. The third stacking structure is located between the first and second stacking structures. The first channel structure extends between the channel layers in the first and third stacking structures. The second channel structure extends between the channel layers in the second and third stacking structures. The gate dielectric layer and the first gate structure wrap around the first channel structure. The switching layer and the second gate structure wrap around the second channel structure.