Transistor TRIZ Cases

A semiconductor CESL in the epitaxial source/drain controls contact etching, cuts etch loss, and expands contact area in FinFETs.

Different exposure times within same-color pixels under one on-chip lens enable simultaneous phase detection and HDR image capture.

Using a dummy transistor of a different type, this power control circuit cuts ON resistance, frees routing resources, and lowers IC power use.

Selective wet removal of the metal gate leaves high-K dielectric in place, shielding source/drain epi layers during active-edge dry etching.

Field insulating layers and shaped epitaxial fins improve channel control and suppress short-channel effects without longer gates.

A pre-silicide NiSi2 source/drain contact stack enables lower-temperature anneals to limit metal spiking, shorts, threshold shifts, and resistance.

A cured etch-stopper and two-stage dry etching control through-hole depth in oxide semiconductor TFT boards, preventing over-etch damage.

Germanium diffusion into Si nanoribbons boosts hole mobility in gate-all-around transistors while supporting dense 10 nm NMOS and PMOS integration.

Dual-material barrier patterns in stacked transistors block diffusion and preserve electrical isolation as MOSFET dimensions shrink.

A hard insert layer reinforces soft low-k dielectric films, limiting trench deformation and improving interconnect metallization.

Alternating dielectric and capping layers in insulating fins prevent source/drain merging, reduce extrusion defects, and improve CMP control.

Asymmetric gate capacitance and mediated gate control suppress word line noise in capacitor-less DRAM cells, improving read reliability.

An isolation layer blocks dummy source/drain formation in CFET skew cells, replacing it with insulation to cut unwanted cell capacitance.

A shaped source/drain trench fill uses thicker edge insulation and sloped sidewalls to prevent gate shorting while preserving nanosheet performance.

Oxygen addition and heat treatment stabilize the oxide semiconductor layer, reducing transistor variation and improving reliability.

BEI intrusions in GLDD regions reshape the electric field to raise breakdown voltage and suppress punch-through current in scaled MOSFETs.

A deep node through the second substrate shortens FD-to-wiring connections, reducing coupling and improving conversion gain.

A grounded charge balance layer suppresses body diode turn-on and enables negative body bias, raising LDMOS source voltage to about 30 V.

A multilayer transparent electrode stack raises pixel aperture ratio, improving see-through display transparency with controlled layer connections.

A coplanar PIN sensing stack improves light collection and suppresses noise light interference for more accurate in-display fingerprint authentication.

Using mandrel-spacer patterning, this case improves fin-end isolation trench depth control and widens the etch window for sub-10 nm layouts.

Selective RuSi on pFETs plus TiSi on both transistors lowers Schottky barrier height and contact resistance without extra lithography.

Recessed insulation and electrode interfaces create anchor effects that preserve assembly quality while improving lateral stress tolerance.

Oxidation followed by epitaxial cap growth enlarges FinFET fins, reducing fin top loss, gate voids, and non-uniform gate length.

An amorphous buried layer and insulating structures raise substrate impedance to curb parasitic currents and simplify RF chip fabrication.

A trench-isolated avalanche photodiode array with well regions and microlenses raises aperture ratio while reducing optical crosstalk in LiDAR.

A planar write-read transistor layout removes the capacitor to raise memory cell density while preserving signal storage and readout.

Multiple switching channels are integrated on one nitride chip to remove PCB parasitics, cut board area, and improve power supply reliability.

Fine-pitch backside interconnects are preformed on a carrier substrate to improve overlay control, shrink critical dimensions, and cut defects.

Using Si and SiGe dual-fin FinFETs with continuous and discontinuous fins, this case balances SRAM read-write speed, write margin, and leakage.

Backside die contacts and conductive clips free front-side area for high-current LDFET package connections while easing manufacturability.

Multiple bootstrap capacitors and diode paths maintain drive voltage for synchronous series switching while preventing overvoltage breakdown.

SiC and SiGeC barrier layers with a wavy interface block source/drain leakage in tightly integrated FinFET structures and improve transistor operation.

A buried active contact with expansion and vertical extension portions increases source/drain contact area to cut resistance in scaled MOSFETs.

A stepped isolation boundary with a slanted supporting layer reduces residue contamination, isolation damage, and dishing between HV and LV regions.

A dielectric mold acts as an etch stop during fin cutting, protecting adjacent fins and widening the process window for dense transistor layouts.

Isolation dummy gates split active regions to raise transistor density while preserving design rule compliance and controlling current leakage.

Low-k dielectric features separate wrapped gate portions in nanosheet transistors to cut capacitance and improve speed and power efficiency.

Vertically stacked nanostructures and controlled source/drain depth raise computing power without added substrate area or design complexity.

Insulating strips replace dummy gates between power transmission cell regions to block leakage and improve backside power rail routing.

A back-side through-substrate via and laterally extended well layout support denser FinFET scaling while preserving precise fin and isolation formation.

NAND, NOR, and stacked gate paths cut sensitive nodes and raise critical charge collection, reducing single-event upsets in flip-flops.

A liner epitaxial layer in GAA FETs blocks gate-source/drain bridging and improves channel control at sub-10-15 nm nodes.

A carbon-containing source/drain buffer layer blocks dopant diffusion into the FinFET channel, lowering resistance while preserving mobility.

Etch-resistant spacers and trimmed isolating fins improve gate-to-source/drain isolation, reducing shorts, voids, and bridging.

A bias circuit drives a shared n-well to the higher supply, enabling compact level shifting across power domains while reducing latch-up risk.

A dynamic gate bias circuit holds pass-switch resistance nearly constant to block overvoltage while preserving rail-to-rail signal linearity.

Offset backside power rails avoid overlap with GAA active regions, preserving source-drain signals for more accurate interconnect defect analysis.

Polar sidewall interfaces in a fin-based III-nitride FET-TFET structure enable low-voltage tunneling, higher density, and lower off-current.