Dual-Fin FinFET SRAM Layout for Read-Write Speed Balance

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Solution Overview

Problem

The increasing complexity and miniaturization of Static Random Access Memory (SRAM) cells in integrated circuits pose challenges in achieving high read and write speed, making it difficult to meet demanding performance requirements.

Innovation Solution

The use of dual-fin FinFETs with different semiconductor fin materials (Si and SiGe) for logic and memory cells, where logic cells have continuous fin lines for improved performance and memory cells have discontinuous fin lines for enhanced write margin, allowing for deeper junctions in logic cells and shallower junctions in memory cells to optimize speed and write performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If SRAM cells are downscaled to increase functional density, then the number of cells per chip area increases, but read and write speed deteriorate

Engineering Contradiction:

Improvefunctional densityVSAvoidread and write speed

Core Design Contradiction:

Quantity of substanceVSSpeed

Solution Approach 1:

The patent applies local quality by using different fin material compositions in different regions of the IC. Logic cells use continuous fin lines with one material composition optimized for speed, while memory cells use discontinuous fin lines with different material composition optimized for write margin. This allows each region to have locally optimized properties rather than uniform design.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent segments the IC into distinct logic cell regions and memory cell regions with different fin structures. Logic cells have continuous fin lines while memory cells have discontinuous fin lines, allowing independent optimization of each segment's performance characteristics.

Inventive Principle:

Principle #1Segmentation

2Speed

If continuous fin lines are used in memory cells to improve read speed, then read speed increases, but write margin deteriorates

Engineering Contradiction:

Improveread speedVSAvoidwrite margin

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

Memory cells use discontinuous fin lines with material composition optimized for write margin rather than continuous fin lines. This local optimization ensures reliable write operations while accepting slightly reduced read speed compared to continuous fin design.

Inventive Principle:

Principle #3Local quality

3Speed

If deeper junctions are used in logic cells to improve performance, then logic cell speed increases, but manufacturing precision requirements increase

Engineering Contradiction:

Improvelogic cell speedVSAvoidjunction depth control

Core Design Contradiction:

SpeedVSManufacturing precision

Solution Approach 1:

The patent changes the material composition parameter of the fin lines (using SiGe for logic cells and Si for memory cells) to achieve different electrical characteristics. This allows logic cells to achieve high performance through material properties rather than solely relying on deeper junctions, thereby reducing manufacturing precision requirements.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12159872B2IC including standard cells and SRAM cells

Publication Date: 2024.12.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An IC is provided. The IC includes a first P-type FinFET and a second P-type FinFET. The first P-type FinFET includes a silicon germanium channel region. The second P-type FinFET includes a Si channel region. First source/drain regions of the first P-type FinFET are formed on a discontinuous semiconductor fin, and second source/drain regions of the second P-type FinFET are formed on a continuous semiconductor fin. A first depth of the first source/drain regions is different from a second depth of the second source/drain regions.