Power Control Circuit Layout Using Mixed Transistor Types
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Solution Overview
Problem
Current integrated circuit (IC) designs face challenges in minimizing power consumption, particularly when functional circuits are in non-active states, as existing approaches do not efficiently manage power supply nodes and routing resources.
Innovation Solution
Incorporating a header circuit and/or footer circuit with a first and second transistor of different types, where the second transistor is electrically coupled as a dummy transistor, allowing for efficient power control and freeing up routing resources, thereby reducing ON resistance and increasing power current density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-type transistor is used in header/footer circuits, then the design is simpler, but routing resources are not optimized and ON resistance remains higher
Solution Approach 1:
The patent combines two different transistor types (first transistor and second transistor with different channel widths) into a single header/footer circuit configuration. This merging allows the circuit to simultaneously achieve good routing resource utilization and low ON resistance, resolving the contradiction between design simplicity and power control efficiency.
Solution Approach 2:
The patent applies different transistor types with different local characteristics (different channel widths) to different positions within the header/footer circuit. The first transistor has a first channel width optimized for certain routing conditions, while the second transistor has a second channel width optimized for other conditions, allowing each component to contribute optimally to overall power control efficiency.
2Area of stationary object
If routing resources are not optimized, then chip area is larger, but power current density is reduced
Solution Approach 1:
The patent changes the parameter of transistor channel width by introducing two different transistor types with different channel widths. This parameter variation allows optimization of routing resource utilization, which in turn increases power current density without requiring additional chip area, effectively resolving the contradiction between chip area and power current density.
3Loss of energy
If ON resistance is not reduced, then power consumption is higher, but transistor configuration is simpler
Solution Approach 1:
The patent merges two different transistor types in the header/footer circuit to achieve low ON resistance and reduced power consumption. The combination of transistors with different channel widths creates a configuration that optimizes current flow, reducing power loss while maintaining manageable design complexity through systematic integration.
Data Source
AI summary
An integrated circuit (IC) device includes a power control circuit including a first transistor and a second transistor of different types. The first transistor includes a gate terminal configured to receive a control signal, a first terminal electrically coupled to a first power supply node, and a second terminal electrically coupled to a second power supply node. The second transistor includes a gate terminal configured to receive the control signal, and first and second terminals configured to receive a predetermined voltage. The first transistor is configured to, in response to the control signal, connect or disconnect the first and second power supply nodes.