Capacitor-Less Memory Cell Layout Using Planar Write-Read Transistors
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Solution Overview
Problem
As semiconductor memory devices shrink in size, maintaining high integration and capacity while reducing the size of memory cells poses a challenge, particularly in minimizing the space occupied by capacitors and optimizing the arrangement of transistors.
Innovation Solution
The semiconductor device incorporates a write transistor and a read transistor with specific layer configurations over a substrate, including word lines, gate dielectric layers, channel layers, and bit lines, allowing for dense arrangement and capacitor-less memory cells, enabling efficient signal storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional one transistor and one capacitor (1T-1C) structure is used, then signal storage function is achieved, but the capacitor occupies large space reducing memory cell density
Solution Approach 1:
The patent extracts and removes the capacitor component from the traditional 1T-1C memory cell structure, creating a capacitor-less memory cell that uses only transistors for signal storage. This elimination of the capacitor directly resolves the space occupation problem while maintaining the essential signal storage function through alternative transistor-based mechanisms.
Solution Approach 2:
The patent makes the transistor serve multiple functions - it acts as both the access transistor and the storage element by utilizing the transistor's inherent capacitance and charge storage capabilities. This multi-functionality allows the single transistor to replace the traditional combination of transistor plus capacitor, thereby increasing memory cell density.
2Productivity
If feature size of semiconductor memory device is decreased, then device integration is improved, but available space for memory cell decreases
Solution Approach 1:
The patent utilizes three-dimensional vertical stacking of transistor layers to create memory cells that extend in the vertical dimension rather than only occupying horizontal plane space. This dimensional transition allows multiple memory cells to be stacked vertically, effectively increasing device integration while maintaining adequate space for each memory cell.
Solution Approach 2:
The patent implements nested transistor structures where transistors are arranged in overlapping and stacked configurations, with lower-layer transistors serving multiple functions for upper-layer cells. This nesting approach maximizes the use of available space by allowing memory cells to share common structures and pathways.
Data Source
AI summary
A semiconductor device according to an embodiment of the present disclosure includes a write transistor and a read transistor disposed over a substrate. The write transistor includes a write word line disposed on a plane that is substantially parallel to a surface of the substrate over the substrate, a write gate dielectric layer disposed over the write word line, a write channel layer disposed over the write gate dielectric layer, and a write bit line disposed over the substrate and extending in a direction substantially perpendicular to a surface of the substrate, and electrically connected to one end of the write channel layer. The read transistor includes a read channel layer disposed on the plane over the substrate, a read gate dielectric layer disposed over the read channel layer, and a read gate electrode layer disposed over the read gate dielectric layer and electrically connected to the other end of the write channel layer.