Shared N-Well Level Shifter Layout for Latch-Up Prevention
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Solution Overview
Problem
Integrated circuits with multiple power domains face challenges in efficiently shifting logical levels between different power supply voltage levels, often requiring multiple transistors and separate n-wells, which can lead to increased space requirements and latch-up risks.
Innovation Solution
A level shifting circuit with a bias circuit that biases a common n-well based on the greater of two power supply voltage levels, using PMOS transistors positioned in the common n-well to avoid latch-up risks while reducing space requirements by eliminating the need for separate n-well spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PMOS transistors are placed in separately biased n-wells for level shifting between power domains, then latch-up risks are reduced, but the space requirements increase significantly
Solution Approach 1:
The patent combines multiple PMOS transistors that operate in different power domains into a single shared n-well structure. This merging eliminates the need for separate n-wells for each power domain, significantly reducing the total area occupied by level shifters while maintaining proper electrical isolation through shared well biasing circuits.
Solution Approach 2:
The shared n-well structure serves multiple functions simultaneously: it hosts PMOS transistors from different power domains, provides a common reference potential, and enables level shifting between multiple voltage domains through a single unified structure rather than requiring separate dedicated structures for each function.
2Reliability
If separate n-wells are used for PMOS transistors in different power domains, then electrical isolation is improved, but device complexity increases
Solution Approach 1:
Multiple n-well structures are merged into a single shared n-well that accommodates PMOS transistors from different power domains. This reduction in the number of separate n-wells simplifies the overall device structure and manufacturing process while electrical isolation is maintained through shared well biasing circuits that provide appropriate potential references.
3Ease of manufacture
If level shifters use traditional separate n-well configuration, then manufacturing processes are well-established, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges multiple n-well formation steps into a single shared n-well structure, eliminating the need for precise spacing and alignment between multiple separate n-wells. This approach maintains compatibility with standard CMOS manufacturing processes while significantly reducing the precision requirements for n-well placement and spacing.
Data Source
AI summary
A method of generating an integrated circuit (IC) layout diagram includes defining first through fourth PMOS transistors in an n-well region, arranging a plurality of conductive regions whereby a bias circuit is configured to include the first and second PMOS transistors and a level shifter is configured to include the third and fourth PMOS transistors, and arranging a plurality of conductive elements whereby a first power domain includes electrical connections to each of the first and third PMOS transistors and a second power domain includes electrical connections to each of the second and fourth PMOS transistors.