Fin Jog Structure With Epitaxial Cap for Fin Top Loss Reduction
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Solution Overview
Problem
In semiconductor integrated circuit (IC) manufacturing, particularly in FinFET and multi-bridge-channel transistor designs, issues such as fin top loss, footing profile, voids in dummy gates, and non-uniform gate lengths lead to defects and performance degradation due to the scaling down of IC devices, affecting yield and operational parameters like speed and power consumption.
Innovation Solution
A method involving oxidation and epitaxial growth to form a cap layer on exposed surfaces of fins and dummy gate structures, which enlarges the fin uncovered by the dummy gate, reduces void sizes, and prepares the structure for replacement with a metal gate, thereby addressing fin top loss and gate non-uniformity issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but footing profile, voids in polysilicon gate, and excessive fin top loss occur causing defects
Solution Approach 1:
The patent applies preliminary action by performing oxidation on the fin structure before gate formation to create an oxide layer that prevents footing profile and fin top loss during subsequent processing steps. This pre-treatment ensures the fin structure maintains its integrity throughout the manufacturing process, eliminating defects that would otherwise occur at smaller geometries
Solution Approach 2:
The patent changes physical parameters by introducing oxidation treatment that modifies the fin surface properties. The oxide layer formed through this parameter change prevents material loss and footing profile, allowing successful fabrication at reduced geometry sizes while maintaining manufacturing precision
2Device complexity
If gate critical dimensions are reduced to increase functional density, then more circuits can be integrated, but voids in polysilicon gate and footing profile are introduced yielding defects
Solution Approach 1:
The oxidation process is performed as a preliminary action before gate formation, creating a protective oxide layer on the fin structure. This pre-treatment prevents the formation of voids and footing profile that would otherwise occur when reducing gate critical dimensions, thereby maintaining device reliability despite increased circuit integration density
Solution Approach 2:
The oxide layer acts as an intermediary between the fin structure and the polysilicon gate material. This intermediate layer prevents direct interaction that would cause voids and footing profile, allowing the gate to be formed at reduced critical dimensions without compromising device reliability
3Reliability
If fin top loss is reduced to improve device performance, then current flow is enhanced, but additional processing steps are required increasing manufacturing complexity
Solution Approach 1:
The patent merges the oxidation process with existing manufacturing steps, integrating fin structure preparation into the standard fabrication flow. By combining the protective oxide formation with gate formation or source/drain processing, the solution enhances current flow without adding significant manufacturing complexity
Solution Approach 2:
The oxidation process is self-service in that it automatically forms the protective oxide layer on exposed fin surfaces without requiring additional masking or patterning steps. The process inherently protects only the necessary regions, reducing fin top loss and improving device performance through a self-limiting chemical reaction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances current driving capability, reduces defects, and improves operating parameters by vertically and horizontally enlarging fins and eliminating footing portions and voids, leading to better performance and reduced electrical shorts in the semiconductor devices.
Implementation Method 1
performing an oxidizing process to exposed surfaces of the fin and the dummy gate structure to form an oxide layer thereon
Implementation Method 2
epitaxially growing a cap layer on the unoxidized top surface and sidewalls of the fin and the unoxidized sidewalls of the dummy gate structure
Data Source
AI summary
A method includes providing a workpiece. The workpiece includes a substrate, a fin protruding from the substrate, and a dummy gate structure over the fin. The method further includes performing an oxidizing process to exposed surfaces of the fin and the dummy gate structure to form an oxide layer thereon, removing the oxide layer to expose an unoxidized top surface and sidewalls of the fin and unoxidized sidewalls of the dummy gate structure, epitaxially growing a cap layer on the unoxidized top surface and sidewalls of the fin and the unoxidized sidewalls of the dummy gate structure, forming a source/drain feature on the fin, and replacing the dummy gate structure with a metal gate structure.