Nanosheet Source/Drain Trench Layout to Prevent Gate Shorting
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Solution Overview
Problem
The existing semiconductor devices face challenges in preventing short-circuits between the source/drain region filling layer and the gate electrode, and in optimizing the performance of the source/drain region to enhance device performance.
Innovation Solution
The semiconductor device design includes a substrate with active patterns and nanosheets, where a gate electrode surrounds the nanosheets, and a source/drain region with a first layer along the trench walls and a second layer filling the trench, with specific thickness and width variations to prevent short-circuits and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the second layer fills the source/drain trench completely, then the source/drain region performance is improved, but the risk of short-circuit between the second layer and gate electrode increases
Solution Approach 1:
The first layer is designed with non-uniform thickness, being thicker at the edges adjacent to the gate electrode and thinner at the center. This local variation in thickness provides enhanced insulation where the short-circuit risk is highest (near the gate electrode) while maintaining adequate filling in the center region for optimal source/drain performance.
2Productivity
If the second layer is made thicker to increase source/drain region performance, then the performance is improved, but the distance to the gate electrode decreases increasing short-circuit risk
Solution Approach 1:
The first layer thickness is locally optimized to be greater at the edges adjacent to the gate electrode and smaller at the center. This creates a thickness gradient that maintains adequate spacing from the gate electrode where needed while allowing the second layer to extend closer to the gate in the center region, thereby maximizing source/drain performance without compromising reliability.
Data Source
AI summary
A semiconductor device includes a substrate. An active pattern extends in a first horizontal direction on the substrate. First to third nanosheets are sequentially spaced apart from each other in a vertical direction on the active pattern. A gate electrode extends in a second horizontal direction on the active pattern and surrounds the first to third nanosheets. A source/drain region includes a first layer disposed along side walls and a bottom surface of a source/drain trench and a second layer filling the source/drain trench. The second layer includes a first lower side wall facing a side wall of the first nanosheet and an opposite second lower side wall. A lower surface connects the first and second lower side walls and extends in the first horizontal direction. The first and second lower side walls of the second layer extend to have a constant slope in opposite directions to each other.