Stacked Transistor Barrier Structure for MOSFET Scaling Reliability
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operation characteristics, necessitating improved methods for fabricating semiconductor devices with enhanced performance.
Innovation Solution
A semiconductor device design featuring stacked transistors with distinct barrier patterns made of different materials, which serve as potential barriers between source/drain patterns, allowing for improved strain management and electrical isolation between transistors, facilitating easier fabrication and enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for smaller pattern sizes, then device density and integration are improved, but operation characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional stacked transistor structures. Multiple transistors are stacked vertically to form a column structure, effectively utilizing the third dimension (depth) to increase device density without further reducing the lateral pattern size. This dimensional transition allows maintaining operation characteristics while achieving higher integration.
Solution Approach 2:
The stacked transistor structure is divided into multiple independent transistor units stacked vertically. Each transistor unit has its own gate electrode, channel, and source/drain regions. The barrier patterns are also segmented into first and second barrier patterns with different materials, allowing independent optimization of each segment's properties to maintain performance despite scaling.
2Device complexity
If stacked transistors are fabricated with simple barrier patterns, then manufacturing complexity is reduced, but electrical isolation and strain management deteriorate
Solution Approach 1:
Different barrier patterns are applied at different locations within the stacked transistor structure. The first barrier pattern (e.g., silicon oxide) and second barrier pattern (e.g., silicon nitride) have different material properties optimized for specific functions: one provides electrical isolation while the other provides strain management. This local differentiation of material properties enables simultaneous optimization of electrical isolation and strain management without increasing overall structural complexity.
Solution Approach 2:
The barrier structure uses composite materials consisting of multiple layers with different properties. By combining materials like silicon oxide and silicon nitride in a stacked configuration, the system achieves both electrical isolation (from one material) and strain management (from another material) within a single integrated barrier structure, resolving the contradiction between simplicity and performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the fabrication of semiconductor devices with improved performance by preventing diffusion and ensuring electrical disconnection between transistors, thereby maintaining transistor integrity and efficiency.
Implementation Method 1
a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns
Data Source
AI summary
A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. The first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.