Capacitor-Less DRAM Cell Structure for Word Line Noise Isolation
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Solution Overview
Problem
Capacitive coupling between the word line and the floating body in capacitor-less single-transistor DRAMs causes direct noise transmission, leading to erroneous reading or rewriting of storage data, making it difficult to commercially introduce such DRAMs.
Innovation Solution
A memory device with a structure comprising a semiconductor base material, impurity layers, gate insulating layers, and gate conductor layers, where the gate capacitance of one gate conductor layer is larger than the other, allowing controlled page write and erase operations, and using forced-inversion-type sense amplifier circuits for page read operations to manage memory cell currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitor-less single-transistor DRAM structure is used, then device integration density is improved, but noise transmission causes erroneous reading or rewriting of storage data
Solution Approach 1:
The patent introduces a plate line as an intermediary element that couples to the floating body through a gate insulating layer. This plate line acts as a mediator to transmit control signals while isolating the word line from direct capacitive coupling with the floating body, thereby reducing noise transmission and enabling reliable data storage in high-density capacitor-less DRAM structures
Solution Approach 2:
The patent transitions from conventional planar transistor structures to vertical SGT (Stacked Gate Transistor) structures where the channel extends in a direction perpendicular to the substrate surface. This dimensional change enables higher integration density while the vertical stacking of gate conductor layers provides additional control dimensions for managing noise and signal transmission
2Speed
If word line voltage is changed for data reading or writing, then data access speed is improved, but capacitive coupling transmits voltage changes as direct noise to floating body
Solution Approach 1:
The plate line serves as an intermediary that decouples the direct capacitive relationship between the word line and floating body. When the word line voltage changes during read/write operations, the plate line mediates the signal transmission through its gate insulating layer coupling, preventing direct noise transmission to the floating body while maintaining fast data access speeds
Solution Approach 2:
The gate control structure is segmented into multiple independent gate conductor layers (first gate conductor layer connected to word line, second gate conductor layer connected to plate line). This segmentation allows independent control of signal transmission and noise isolation, enabling fast voltage changes on the word line without directly coupling noise to the floating body
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces noise transmission during word line voltage changes, providing a sufficient margin between '1' and '0' potentials, enabling reliable data storage and improving the commercial viability of capacitor-less single-transistor DRAMs.
Implementation Method 1
capacitive coupling between the word line and the floating body is strong. When the potential of the word line is changed at the time of data reading or at the time of data writing, the change is transmitted as direct noise to the floating body
Implementation Method 2
accelerated electrons that flow from the source N+ layer 103 toward the drain N+ layer 104 collide with the Si lattice, and with kinetic energy lost at the time of collision, electron-positive hole pairs are generated (impact ionization phenomenon)
Data Source
AI summary
A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line, the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a first driving control line, and the bit lines are connected to sense amplifier circuits with a switch circuit therebetween. In a page read operation, page data in a group of memory cells selected by the word line is read to the sense amplifier circuits, and in a page addition read operation, at least two sets of page data selected by at least two word lines in multiple selection are added up for each of the bit lines and read to a corresponding one of the sense amplifier circuits.