Buried Active Contact Structure for Low-Resistance MOSFET Scaling
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deteriorated operational properties, necessitating improvements in electric characteristics to maintain performance.
Innovation Solution
A semiconductor device design featuring a substrate with active and source/drain patterns, a gate electrode, and active contacts with buried and expansion portions, where the active contacts include a buried portion buried in the source/drain pattern and a contact portion extended toward an interconnection line, utilizing silicon and germanium to enhance conductivity and reduce electric resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for small pattern size, then pattern size is reduced, but operational properties deteriorate
Solution Approach 1:
The active contact structure transitions from a conventional planar contact to a three-dimensional structure with a buried portion extending vertically into the source/drain pattern. This vertical dimensionality increase compensates for the reduced horizontal pattern size, maintaining adequate contact area and electrical performance despite device scaling.
Solution Approach 2:
The active contact is nested within the source/drain pattern through the buried portion that extends into the source/drain region. This nested configuration increases the contact area without increasing the overall device footprint, allowing improved electrical characteristics while maintaining scaled-down dimensions.
2Reliability
If active contact buried portion is expanded to increase contact area, then electrical resistance is reduced, but device complexity increases
Solution Approach 1:
The active contact is segmented into distinct functional portions: a buried portion that extends vertically into the source/drain pattern to maximize contact area and reduce resistance, and a contact portion that extends upward to connect with interconnection lines. This segmentation allows each portion to be optimized for its specific function while maintaining overall structural integrity.
Solution Approach 2:
The contact structure exhibits local quality variations with the buried portion having a larger cross-sectional area for low resistance contact, and the contact portion having a smaller area for proper interconnection alignment. This localized optimization of geometric properties at different vertical positions achieves both low resistance and manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves electric characteristics by increasing contact area and reducing resistance between the active contacts and source/drain patterns, thereby enhancing the operational speed and performance of semiconductor devices.
Implementation Method 1
The source/drain pattern may include silicon (Si), an impurity allowing the source/drain pattern to have an n-type, and germanium (Ge). A concentration of the germanium (Ge) of the source/drain pattern may increase in a direction from the channel pattern toward the buried portion.
Data Source
AI summary
A semiconductor device includes a substrate including an active pattern, a channel pattern and a source/drain pattern on the active pattern, a gate electrode provided on the channel pattern and extended in a first direction, and an active contact coupled to the source/drain pattern. The active contact includes a buried portion buried in the source/drain pattern and a contact portion on the buried portion. The buried portion includes an expansion portion provided in a lower portion of the source/drain pattern and a vertical extension portion connecting the contact portion to the expansion portion.