FinFET Source/Drain Epitaxy with Semiconductor Etch Stop Layer

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Solution Overview

Problem

As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components into a given area, including issues with etching losses and contact resistance in FinFETs, which affect performance and integration density.

Innovation Solution

A multi-layered epitaxial source/drain region is grown with an intermediate epitaxial layer acting as a semiconductor contact etch stop layer (CESL) to protect underlying layers and control etching during source/drain contact formation, increasing contact area and reducing etching losses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If feature size is reduced to increase integration density, then more components can be integrated into a given area, but etching losses and contact resistance increase

Engineering Contradiction:
Improveintegration densityVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The source/drain structure is segmented into multiple epitaxial layers with different materials and doping concentrations. The first epitaxial layer has lower doping concentration while the second epitaxial layer has higher doping concentration, creating distinct functional zones that optimize both contact resistance and etching control

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the source/drain structure are assigned different material compositions and doping concentrations. The first epitaxial layer uses one material composition optimized for low contact resistance, while the second epitaxial layer uses a different material composition optimized for etching stop functionality, allowing each region to perform its specific function optimally

Inventive Principle:
Principle #3Local quality

2Productivity

If feature size is reduced to increase integration density, then more components can be integrated into a given area, but etching losses increase

Engineering Contradiction:
Improveintegration densityVSAvoidetching losses
Core Design Contradiction:
ProductivityVSLoss of substance

Solution Approach 1:

The first epitaxial layer is formed as a preliminary protective structure before the etching process. This layer acts as a pre-established barrier that prevents excessive etching into the underlying substrate, allowing the etch process to be performed with controlled material removal

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The first epitaxial layer serves as an intermediary between the etching process and the underlying substrate. It absorbs and controls the etching action, preventing direct and excessive etching of the substrate while still allowing the etch process to proceed effectively

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the performance of FinFETs by enhancing contact area and reducing etching losses, thereby increasing operating current and integration density.

Implementation Method 1

A multi-layered epitaxial source/drain region is grown with an intermediate epitaxial layer acting as a semiconductor contact etch stop layer (CESL)

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS12165929B2Semiconductor device and method
Publication Date: 2024.12.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12165929B2 patent drawing
  • US12165929B2 patent drawing
  • US12165929B2 patent drawing

AI summary

In an embodiment, a device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source/drain region including: a main layer in the first fin and the second fin, the main layer including a first semiconductor material, the main layer having an upper faceted surface and a lower faceted surface, the upper faceted surface and the lower faceted surface each being raised from respective surfaces of the first fin and the second fin; and a semiconductor contact etch stop layer (CESL) contacting the upper faceted surface and the lower faceted surface of the main layer, the semiconductor CESL including a second semiconductor material, the second semiconductor material being different from the first semiconductor material.