FinFET Barrier Layer Structure for Leakage Current Isolation
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Solution Overview
Problem
As semiconductor devices become more integrated and complex, they face challenges in reducing leakage current and improving performance, particularly in Fin-type FETs where the narrow width and close separation distances lead to increased operating limitations.
Innovation Solution
The semiconductor device design incorporates a lower barrier layer made of silicon-carbon (SiC) material with a wavy upper surface and an upper barrier layer of silicon-germanium-carbon (SiGeC) material, along with channel layers of undoped silicon, to effectively reduce leakage current between source/drain regions and fins, enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration of semiconductor devices is increased to meet demand for high performance and high speed, then productivity and functionality are improved, but leakage current from source/drain regions increases
Solution Approach 1:
A barrier layer comprising multiple layers with different materials (first barrier layer with first material, second barrier layer with second material having wider bandgap) is introduced as an intermediary between the source/drain regions and the fin. This multi-layer barrier structure effectively blocks leakage current while allowing the high-density integration to proceed, resolving the contradiction between integration density and leakage current reduction.
Solution Approach 2:
The barrier layer is constructed using composite material structure with at least two different materials having different bandgap energies. The combination of materials with different properties (narrower bandgap for structural integration, wider bandgap for leakage blocking) creates an effective barrier against leakage current while maintaining the benefits of high integration density.
2Reliability
If Fin-type FETs with three-dimensional channel structure are used to overcome planar MOSFET limitations, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The barrier layer is segmented into multiple layers (first barrier layer and second barrier layer) with different materials and functions. This segmentation allows each layer to be optimized for specific purposes while collectively solving the leakage current problem in Fin-type FETs, managing the manufacturing complexity through modular layer design.
Solution Approach 2:
Different regions of the barrier layer have different material compositions and properties tailored to local requirements. The first barrier layer and second barrier layer have distinct materials selected for their specific electrical and structural properties, allowing localized optimization to achieve overall device performance while managing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces leakage current and improves the overall performance of semiconductor devices by preventing current leakage between source/drain regions and fins, thereby enhancing the operational efficiency of transistors.
Implementation Method 1
a lower barrier layer on the fin... effectively reduce leakage current between source/drain regions and fins
Implementation Method 2
an upper surface of the lower barrier layer has a wavy shape
Implementation Method 3
an upper barrier layer of silicon-germanium-carbon (SiGeC) material... preventing current leakage between source/drain regions and fins
Data Source
AI summary
A semiconductor device includes; a first fin vertically protruding from a substrate and extending in a first horizontal direction, a second fin vertically protruding from the substrate, an isolation layer contacting side surfaces of the first fin and the second fin, a first lower barrier layer on the first fin, a second lower barrier layer on the second fin, source/drain regions spaced apart in the first horizontal direction on the first lower barrier layer, channel layers disposed between the source/drain regions and vertically spaced apart on the first barrier layer, a gate structure intersecting the first lower barrier layer, surrounding each of the channel layers, and extending in a second horizontal direction, an upper barrier layer on the second lower barrier layer, and first semiconductor layers and second semiconductor layers stacked on the upper barrier layer.