Multi-Gate Active-Edge Etching With High-K Dielectric Protection
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Solution Overview
Problem
Existing semiconductor manufacturing processes, such as the continuous poly on diffusion edge (CPODE) process, often damage source/drain epitaxial layers during etching, compromising device performance and reliability due to weak spots between nanowire/nanosheet channels and inner spacers.
Innovation Solution
A modified CPODE process is introduced where the metal gate etching process selectively removes the metal gate layer without the high-K dielectric, using a wet etching process with ammonium hydroxide, hydrogen peroxide, and water, ensuring the high-K dielectric remains to protect the source/drain epi layers during the CPODE dry etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a CPODE process is used to scale the contacted poly pitch, then gate pitch reduction and device density improvement are achieved, but source/drain epitaxial layers are damaged during etching
Solution Approach 1:
The patent applies preliminary action by forming a protective coating on the source/drain epitaxial layers before the CPODE etching process. This coating is deposited in advance to prevent etchant damage to the epi layers during the subsequent isolation trench etching, thereby enabling pitch scaling while preserving layer integrity.
Solution Approach 2:
The protective coating acts as an intermediary layer between the etchant and the source/drain epitaxial layers. This intermediate protective layer prevents direct contact between the harmful etchant and the sensitive epi layers, allowing the CPODE process to proceed without damaging the critical semiconductor structures.
2Productivity
If continuous scaling of gate pitch is pursued, then device miniaturization and production efficiency improvement are achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: forming the protective coating, performing the CPODE etching, and removing the coating. This segmentation allows each step to be optimized independently and enables the complex scaling process to be managed through systematic, modular process steps rather than a monolithic complex operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates damage to source/drain epi layers, enhancing device performance and reliability by enlarging the CPODE process window and maintaining the integrity of the high-K dielectric layer.
Implementation Method 1
performing a metal gate etching process to remove the metal gate layer from the dummy GAA structure. The metal gate etching process may include a wet etch composed of a combination of ammonium hydroxide, hydrogen peroxide, and water.
Implementation Method 2
The unremoved high-K dielectric may provide another layer, in addition to the interfacial layer, to resist the CPODE dry etching process and effectively mitigate weak spots
Implementation Method 3
performing a CPODE dry etching process to form an isolation trench along the active edge
Data Source
AI summary
A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.