Stacked Nanostructure Transistors With Tunable Channel Widths
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Solution Overview
Problem
Integrated circuits face challenges in increasing computing power while maintaining area efficiency, as existing methods to enhance transistor density often result in increased design complexity and area penalties.
Innovation Solution
The use of nanostructure transistors with adjustable effective channel widths is achieved by stacking semiconductor nanostructures and controlling the depth of source/drain regions through epitaxial growth, allowing for both high-speed and low-power devices to be formed without increasing substrate area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional methods are used to increase transistor density, then computing power increases, but design complexity and area penalties increase
Solution Approach 1:
The channel region is segmented into multiple discrete semiconductor nanostructures (nanowires, nanosheets, or quantum dots) stacked vertically. Each nanostructure acts as an independent channel, allowing the transistor to achieve higher effective channel width and improved performance without increasing the lateral footprint, thereby avoiding area penalties while maintaining design simplicity
Solution Approach 2:
The invention transitions from conventional two-dimensional planar transistors to three-dimensional vertically-stacked nanostructure transistors. By stacking multiple semiconductor nanostructures in the vertical dimension, the effective channel width is increased without occupying additional substrate area, thus improving computing power while avoiding area penalties associated with conventional density increase methods
2Productivity
If conventional methods are used to increase transistor density, then computing power increases, but area usage increases
Solution Approach 1:
The invention transitions from conventional two-dimensional planar transistors to three-dimensional vertically-stacked nanostructure transistors. By stacking multiple semiconductor nanostructures in the vertical dimension, the effective channel width is increased without occupying additional substrate area, thus improving computing power while avoiding area penalties associated with conventional density increase methods
Solution Approach 2:
Multiple semiconductor nanostructures are nested vertically within a compact footprint, similar to nested dolls. The stacked configuration allows multiple channel regions to occupy the same lateral space, achieving high transistor density and improved computing power without increasing the substrate area required per transistor
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of integrated circuits with dedicated high-speed and low-power devices without increased design complexity or area overhead, improving device performance and wafer yield.
Implementation Method 1
The depth of the source/drain regions is controlled by selectively performing an epitaxial growth that effectively extends the height of the substrate
Data Source
AI summary
An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source/drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.