Backside Interconnect Layout for Fine-Pitch Overlay Control
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing device size and increasing integration density while minimizing defects, particularly in forming backside interconnect structures for semiconductor devices, as conventional methods struggle with overlay control and critical dimension precision.
Innovation Solution
The method involves forming fine-pitch backside interconnect structures over a carrier substrate, bonding the substrate to these structures, and creating fins and power rails within the substrate, allowing for better overlay control and reduced device size through FEOL processes, which enables the formation of smaller critical dimension features and improves device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form backside interconnect structures, then manufacturing simplicity is maintained, but overlay control and critical dimension precision deteriorate
Solution Approach 1:
The backside interconnect structures are formed preliminarily over a carrier substrate before the semiconductor substrate is thinned and bonded. This preliminary formation allows precise patterning and overlay control to be established early in the process, before subsequent thinning and bonding operations that would otherwise compromise precision.
Solution Approach 2:
The manufacturing process is segmented into distinct stages: forming interconnect structures over a carrier substrate, then thinning and bonding the semiconductor substrate separately. This segmentation allows each stage to be optimized independently, with the interconnect formation occurring on a stable carrier that provides better overlay control.
2Productivity
If device size is reduced to increase integration density, then integration density improves, but manufacturing precision and overlay control worsen
Solution Approach 1:
Fine-pitch interconnect structures with small critical dimensions are formed preliminarily over a carrier substrate where precise overlay control can be maintained. The carrier substrate provides a stable platform for forming these small features before the semiconductor substrate undergoes thinning and bonding, ensuring that critical dimension precision is preserved despite the small scale.
3Ease of manufacture
If backside interconnect structures are formed directly on the substrate, then process steps are reduced, but overlay control and feature precision deteriorate
Solution Approach 1:
A carrier substrate is introduced as an intermediary platform for forming the backside interconnect structures. This carrier substrate acts as a mediator that provides the necessary stability and precision for forming fine-pitch features, while still allowing the final device to be constructed by bonding the semiconductor substrate to this pre-formed interconnect structure.
Data Source
AI summary
Backside interconnect structures having reduced critical dimensions for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure over a front-side of a substrate; a first backside interconnect structure over a backside of the substrate, the first backside interconnect structure including first conductive features having tapered sidewalls with widths that narrow in a direction away from the substrate; a power rail extending through the substrate, the power rail being electrically coupled to the first conductive features; and a first source/drain contact extending from the power rail to a first source/drain region of the first transistor structure.