Integrated Boot Diode Layout for High-Voltage LDMOS Biasing
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Solution Overview
Problem
Fabricating semiconductor components with higher levels of integration and high voltage capabilities is challenging due to limitations in body diode turn-on and maximum source voltage, particularly for depleted mode LDMOS transistors.
Innovation Solution
Incorporating a charge balance layer electrically connected to a ground reference in a depleted mode LDMOS transistor, which eliminates body diode turn-on above 0.7 volts and allows negative biasing of the body with respect to the source, increasing the maximum source voltage without parasitic PNP turn-on to approximately 30 V.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the body diode is integrated into the LDMOS transistor, then device integration is improved, but body diode turn-on occurs above 0.7 volts limiting high voltage capability
Solution Approach 1:
The charge balance layer is segmented into multiple regions (first charge balance layer and second charge balance layer) with different doping types and concentrations. This segmentation allows independent control of different functional regions: the first layer suppresses body diode turn-on while the second layer enables negative body biasing, thereby resolving the contradiction between integration and high voltage capability
Solution Approach 2:
Different regions of the charge balance layer are doped with different types and concentrations of dopants to create localized functional properties. The first charge balance layer region is optimized for preventing body diode conduction, while the second region is optimized for enabling negative body bias, allowing each local region to perform its specific function without interfering with the other
2Power
If the source voltage is increased beyond 7 volts, then power capability is improved, but parasitic PNP turn-on occurs limiting further voltage increase
Solution Approach 1:
The charge balance layer is positioned and doped to preemptively counteract the formation of parasitic PNP junctions before they can turn on. By creating opposite polarity charge regions adjacent to the body region, the invention prevents the electric field conditions necessary for parasitic PNP turn-on, allowing source voltage to exceed 7 volts without triggering parasitic conduction
Solution Approach 2:
The charge balance layer acts as an intermediary structure between the body region and the high voltage environment. This intermediate layer with its specific doping profile mediates the electric field distribution, preventing direct interaction that would cause parasitic PNP turn-on while still allowing the body region to be negatively biased for high voltage operation
Data Source
AI summary
A microelectronic device including an integrated boot diode and a depleted mode LDMOS transistor with a charge balance layer isolated from the body region and electrically in contact with a substrate. The connection of the charge balance layer of the depleted mode LDMOS transistor directly to the substrate or ground reference eliminates body diode turn-on from the body of the transistor to the drain which typically happens above approximately 0.7 volts. In addition, the depleted mode LDMOS transistor may separate a source contact from a body contact which allows a negative bias of the body with respect to the source. Typically, the source voltage is limited to approximately 7 volts before parasitic PNP turn on becomes a factor. By negatively biasing the body with respect to the source, the maximum source voltage of the depleted mode LDMOS transistor without PNP parasitic turn-on may be increased to approximately 30 V.