FinFET Well and Through-Substrate Via Layout for Dense Scaling
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing functional density while reducing geometry size, particularly in the fabrication of FinFET devices, where existing methods struggle to efficiently form semiconductor fins and isolation dielectrics, leading to limitations in device performance and scalability.
Innovation Solution
A method for fabricating FinFET devices involves forming semiconductor fins and isolation dielectrics through a series of deposition and photolithography processes, including the use of sacrificial layers, spacer formation, and chemical mechanical polish (CMP) to achieve precise fin structures and dielectric coverage, followed by epitaxial growth for source/drain features and gate formation, enabling improved fin formation and dielectric recessing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used for forming semiconductor fins and isolation dielectrics, then the manufacturing process is simpler, but functional density cannot be increased and geometry size cannot be reduced
Solution Approach 1:
The fabrication process is divided into multiple sequential stages: forming sacrificial layers, depositing first spacers, removing sacrificial layers, depositing second spacers, and performing selective recessing. Each stage creates more precisely defined fin structures while maintaining process control through modular steps rather than attempting single-step formation.
Solution Approach 2:
Sacrificial layers are formed in advance before the actual fin structures are created. These preliminary sacrificial structures serve as templates that guide subsequent spacer deposition and define the final fin geometry, enabling precise fin formation through preparatory positioning.
2Productivity
If geometry size is reduced to increase functional density, then production efficiency improves, but existing fabrication methods cannot achieve the required precision
Solution Approach 1:
Spacer layers serve as intermediary structures that transfer the pattern from sacrificial layers to the final fin structures. The spacers act as mediators that enable precise geometry definition at reduced dimensions by providing a controlled deposition process that maintains dimensional accuracy even as feature sizes shrink.
Solution Approach 2:
The method employs multiple deposition processes with varying parameters to create spacers of different thicknesses and compositions. By changing deposition parameters such as thickness, material composition, and deposition conditions, the process achieves the required precision for reduced geometry sizes while maintaining scalability for mass production.
3Manufacturing precision
If multi-step deposition and photolithography processes are used, then functional density increases, but manufacturing time and process complexity increase
Solution Approach 1:
Multiple dielectric layers are combined into a unified isolation structure through selective recessing processes. Rather than forming and planarizing separate dielectric layers independently, the method merges first and second spacers into an integrated isolation dielectric structure, reducing the number of separate planarization steps required while maintaining precise dielectric coverage.
Solution Approach 2:
Sacrificial layers are completely removed after serving their patterning function, extracting the temporary structures that enabled precise fin formation. This extraction of sacrificial materials allows the final fin structures to be formed without the constraints of maintaining sacrificial layer integrity, enabling more precise geometry at the cost of additional removal steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the fabrication of FinFET devices by increasing functional density and reducing geometry size, improving device performance and scalability by allowing for more precise control over fin and dielectric structures, thereby addressing the limitations of existing methods.
Implementation Method 1
chemical mechanical polish (CMP) to achieve precise fin structures and dielectric coverage
Implementation Method 2
epitaxial growth for source/drain features
Data Source
AI summary
A semiconductor structure includes a semiconductive substrate, a channel pattern, a gate pattern, source/drain patterns, and a through substrate via. The semiconductive substrate has a well region. The channel pattern is over a front-side of the well region. The gate pattern is around the channel pattern. The source/drain patterns are on the channel pattern and at opposite sides of the gate pattern. The through substrate via extends from a back-side of the semiconductive substrate to a back-side of the well region. From a cross-sectional view, the well region has a portion laterally extending from a first edge of a front-side surface of the through substrate via to a second edge of the front-side surface of the through substrate via.