Backside Power Rail Layout for GAA FET Defect Detection
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Solution Overview
Problem
The existing semiconductor technologies face challenges in conducting failure analysis due to backside power rails absorbing signals from the source and drain of gate-all-around (GAA) FETs, which hinders the detection of defects in interconnect structures.
Innovation Solution
The backside power rail is designed to not overlap with the active region of GAA transistors, allowing signals to be emitted without absorption, enabling accurate failure analysis by using a tester to detect these signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the backside power rail is positioned to electrically couple to the source and drain of GAA FETs, then power delivery is improved, but signal absorption occurs that prevents defect detection
Solution Approach 1:
The backside power rail is segmented into multiple separate rails rather than a single continuous rail. Each power rail is positioned to electrically couple to specific source or drain regions of GAA FETs while maintaining spatial separation. This segmentation allows different power rails to serve different functional regions without overlapping with active transistor regions, enabling both power delivery and signal detection.
Solution Approach 2:
Different regions of the backside of the semiconductor substrate are assigned different functions: some regions contain power rails for power delivery, while other regions are left free of metal structures to allow signal transmission for defect detection. The power rails are locally positioned to couple with source/drain regions while avoiding overlap with active channel regions, creating local functional zones with distinct properties.
2Reliability
If the backside power rail overlaps with the active region of GAA transistors, then electrical coupling is improved, but signal absorption prevents accurate failure analysis
Solution Approach 1:
The solution moves the power delivery function to the backside of the substrate (z-dimension) rather than placing power rails on the frontside in the same plane as active regions. By utilizing the backside dimension, power rails can be positioned to couple with source/drain regions through the substrate thickness without overlapping with active channel regions in the lateral plane, enabling both functions simultaneously.
Solution Approach 2:
The substrate itself acts as an intermediary medium that enables electrical coupling between the backside power rails and the source/drain regions of frontside GAA FETs. The substrate's conductive properties allow power transmission through its thickness, eliminating the need for direct lateral overlap between power rails and active regions while maintaining electrical connection.
3Adaptability or versatility
If metal structures are added to the backside for power delivery, then device functionality is improved, but signal absorption increases making defect detection difficult
Solution Approach 1:
The backside metal layer is segmented into functionally distinct regions: power rail regions that provide electrical coupling to source/drain structures, and detection regions that are free of metal structures to allow signal transmission. This segmentation enables the backside to simultaneously support power delivery functionality and defect detection capability without mutual interference.
Solution Approach 2:
The backside of the substrate serves multiple functions: it provides mechanical support, enables power delivery through segmented power rails, and allows defect detection through metal-free detection regions. By designing the backside structure to accommodate multiple functions in different spatial zones, the device achieves versatility without compromising any single function.
Data Source
AI summary
A semiconductor device and a method of testing the device are disclosed. In one aspect, the semiconductor device includes a first active region that extends along a first lateral direction and includes a plurality of first epitaxial structures. The semiconductor device also includes an interconnect structure that also extends along the first lateral direction and is disposed below the first active region, wherein at least one of the plurality of first epitaxial structures is electrically coupled to the interconnect structure. The interconnect structure includes at least a first portion that offsets from the first active region along a second lateral direction perpendicular to the first lateral direction.