Source/Drain Contact Stack Using Pre-Silicide NiSi2 Against Metal Spiking
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in forming reliable source/drain contacts, particularly with the risk of electrical shorts and undesirable threshold voltage shifts due to metal spiking and the need for high-temperature anneals, which can also increase contact resistance.
Innovation Solution
The formation of a NiSi2 silicide region using a pre-silicide layer at lower anneal temperatures, with a faceted shape to increase surface area and reduce resistance, and the potential addition of silicide alloy regions for thermal stability, all without the need for implanted dopants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature anneals are used to form silicide regions, then reliable source/drain contacts are formed, but electrical shorts and threshold voltage shifts occur due to metal spiking
Solution Approach 1:
A pre-silicide layer is deposited before the main silicide formation process. This preliminary layer acts as a barrier that prevents metal spiking into the semiconductor substrate during subsequent high-temperature annealing, while still allowing controlled silicide formation at the interface.
Solution Approach 2:
The pre-silicide layer serves as an intermediary between the metal silicide layer and the semiconductor substrate. It mediates the interaction by providing a controlled interface that enables silicide formation while blocking harmful metal diffusion into the substrate.
2Object-affected harmful factors
If lower anneal temperatures are used to prevent metal spiking, then electrical shorts are reduced, but contact resistance increases
Solution Approach 1:
The pre-silicide layer is deposited in advance to create a low-resistance pathway. This preliminary structure enables effective silicide formation at lower annealing temperatures by providing a pre-established interface that reduces the thermal activation energy required for silicide formation.
Solution Approach 2:
The deposition parameters of the pre-silicide layer (thickness, composition, deposition rate) are optimized to achieve the right balance between preventing metal spiking and maintaining low contact resistance. The layer thickness is specifically controlled to be sufficient to block spiking but thin enough to allow efficient silicide formation.
3Productivity
If feature sizes are reduced to increase integration density, then more components are integrated, but manufacturing precision and contact formation become more difficult
Solution Approach 1:
The pre-silicide layer is deposited conformally across the entire wafer before patterning, ensuring uniform coverage even at reduced feature sizes. This preliminary conformal deposition is less sensitive to lithography limitations than direct contact hole filling, enabling precise contact formation in scaled devices.
Solution Approach 2:
The pre-silicide layer provides locally optimized properties at the contact interface, with thickness and composition tailored for each specific contact region. This local customization enables precise control of silicide formation characteristics even as overall device dimensions are reduced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the likelihood of electrical shorts and threshold voltage shifts, improves contact resistance, and provides thermal stability while allowing for the formation of NiSi2 silicide regions at lower temperatures, enhancing the performance and reliability of semiconductor devices.
Implementation Method 1
depositing a nickel silicide layer on the semiconductor substrate, and annealing the nickel silicide layer to form a nickel disilicide region
Implementation Method 2
depositing a pre-silicide layer on the semiconductor substrate before depositing the nickel silicide layer
Data Source
AI summary
A device includes a fin extending from a semiconductor substrate, a gate stack over and along a sidewall of the fin, an isolation region surrounding the gate stack, an epitaxial source/drain region in the fin and adjacent the gate stack, and a source/drain contact extending through the isolation region, including a first silicide region in the epitaxial source/drain region, the first silicide region including NiSi2, a second silicide region on the first silicide region, the second silicide region including TiSix, and a conductive material on the second silicide region.