GAA Channel Liner Structure to Prevent Gate-Source/Drain Bridging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor technology advances to sub-10-15 nm nodes, gate-all-around (GAA) FETs face challenges in achieving further improvements due to limitations in transistor design, particularly in controlling current through the channel region, with the bottom side of the channel not being under close gate control.
Innovation Solution
The manufacturing process involves forming fin structures with stacked semiconductor layers, creating a sacrificial gate structure, recessing the sacrificial layers, and forming a liner epitaxial layer to prevent gate electrode and source/drain bridging, allowing for precise control of the channel region with a gate dielectric and gate electrode layer surrounding the channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a Fin FET structure is used with gate electrode adjacent to three side surfaces, then manufacturing complexity is reduced, but gate control over the channel region is insufficient due to the bottom part being far from the gate electrode
Solution Approach 1:
The patent transitions from a planar gate structure (Fin FET) to a three-dimensional gate-all-around structure where the gate electrode completely surrounds the channel region in multiple dimensions. This dimensional change enables the gate to control all surfaces of the channel including the bottom, achieving full depletion and reducing short-channel effects while maintaining manufacturability through advanced fabrication techniques.
2Productivity
If transistor dimensions are scaled down to sub 10-15 nm nodes, then device density and performance are improved, but short-channel effects increase and gate control becomes more difficult
Solution Approach 1:
The patent implements a nested structure where the gate electrode completely surrounds the channel region, with the gate wrapping around all four sides of the channel. This nested configuration ensures that even at sub 10-15 nm dimensions, the gate maintains strong electrostatic control over the entire channel, preventing carrier leakage and reducing short-channel effects while enabling higher device density.
3Manufacturing precision
If a gate-all-around structure is implemented to surround all side surfaces of the channel, then gate control and depletion are improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent divides the gate structure into multiple segments or layers that can be formed separately and then assembled to create the complete gate-all-around structure. This segmentation approach simplifies the manufacturing process by breaking down the complex three-dimensional gate formation into manageable steps, reducing process difficulty while maintaining the precise gate control required for sub-10nm transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances control over the channel region, reducing short-channel effects and improving current handling, thereby advancing the performance of GAA FETs beyond current limitations.
Implementation Method 1
A liner epitaxial layer is formed at least on the recessed surface of the sacrificial layers
Data Source
AI summary
A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers, and a liner semiconductor layer disposed between the first channel layers and the first source/drain region.