3D Memory Arrays with Bidirectional Word-Line and Bit-Line Paths
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Solution Overview
Problem
The increasing demand for data storage capacity in 3D memory devices, particularly for neural network models, has not been adequately addressed, limiting their efficiency and performance in artificial intelligence applications.
Innovation Solution
A 3D memory device design that incorporates multiple 2D memory arrays, encoding circuits, and sensing circuits, allowing signals to be transmitted through both word lines and bit lines, enabling the storage of multiple neural network layers by alternating data transmission directions within the memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional single-path signal transmission is used in 3D memory devices, then the structure is simple, but the data storage capacity is limited
Solution Approach 1:
The patent introduces a second signal transmission dimension by enabling bidirectional communication between word lines and bit lines. Memory cells can receive signals through one line type and output through the other, effectively doubling the data storage capacity without adding physical memory layers. This dimensional transformation resolves the contradiction by expanding functional capacity while maintaining structural simplicity.
Solution Approach 2:
The patent makes word lines and bit lines multi-functional by allowing them to serve both as input and output pathways. Each line type can receive and transmit data in both directions, enabling the same physical structure to handle multiple data streams simultaneously. This multi-functionality increases storage capacity without proportionally increasing device complexity.
2Quantity of substance
If impedance adjustment is used to store neural network data, then computational capability is improved, but the amount of storable data becomes insufficient
Solution Approach 1:
The patent adds a second data transmission dimension by utilizing both word lines and bit lines for bidirectional data flow. This allows the memory device to store and process twice the amount of neural network data while maintaining the same impedance-based computational mechanism, thus resolving the contradiction between storage capacity and computational efficiency.
Solution Approach 2:
The patent divides the data storage and processing function into two parallel pathways: one through word lines and another through bit lines. Each pathway can independently store and compute neural network data, effectively segmenting the computational workload across multiple channels and doubling the overall data throughput.
3Speed
If in-memory computing is implemented, then data reading speed is improved, but the processor spends excessive time and power accessing memory
Solution Approach 1:
The patent introduces bidirectional signal transmission as a second functional dimension, allowing data to be read and processed simultaneously through multiple pathways. This enables in-memory computing operations to execute faster by utilizing both word and bit lines for parallel data access, reducing the time and power the processor needs to spend on memory operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the storage capacity and efficiency of 3D memory devices by effectively storing and processing multiple neural network layers, improving data handling and computational speed.
Implementation Method 1
Each of the plurality of 2D memory arrays is coupled to the plurality of word lines and the plurality of bit lines, configured to receive a first input voltage and output a first output current, and configured to receive a second input voltage and output a second output current
Data Source
AI summary
A three-dimensional (3D) memory device comprising word lines, bit lines, a 3D memory array, encoding circuits and sensing circuits is provided in the present disclosure. The 3D memory array comprises two-dimensional (2D) memory arrays and stores first to fourth neural network data related to at least one neural network model. Each of the 2D memory arrays is coupled to the word lines and the bit lines, and is configured to receive first and second input voltages and output corresponding first and second output currents. The encoding circuits are respectively coupled to the 2D memory arrays and configured to generate the first and second input voltages respectively based on the first and second neural network data. The sensing circuits are respectively coupled to the 2D memory arrays and configured to generate the third and fourth neural network data respectively based on the first and second output currents.