3D Memory Bit Line Coupling for Capacitance Uniformity
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Solution Overview
Problem
High-density 3D memory devices face challenges in achieving low manufacturing costs and reliable bit line capacitance uniformity due to the complexity of lithography steps and varying bit line capacitances across different plane positions in 3D memory arrays.
Innovation Solution
The solution involves shifting the sequences of bit line coupling to different layers in a 3D memory array, ensuring that each bit line is coupled to multiple plane positions across different memory blocks, thereby averaging out the capacitance differences and achieving uniform bit line capacitance across the array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple planes of memory cells are stacked to achieve higher density, then storage capacity increases, but manufacturing costs increase due to multiplied critical lithography steps
Solution Approach 1:
The memory array is divided into multiple memory blocks, where each block contains multiple planes of memory cells. This segmentation allows the array to be organized into manageable units that can be manufactured with controlled lithography complexity while achieving high overall density through stacking multiple blocks.
Solution Approach 2:
The patent transitions from planar 2D memory organization to 3D vertical stacking by introducing multiple planes stacked in the vertical dimension. Each memory block contains planes stacked at different vertical positions, enabling higher storage capacity without proportionally increasing lithography complexity in the lateral plane.
2Adaptability or versatility
If bit lines are coupled to different plane positions in a 3D memory array, then data access capability improves, but bit line capacitance uniformity deteriorates due to varying capacitances at different plane positions
Solution Approach 1:
Different memory blocks are assigned different local coupling sequences for their bit lines to plane positions. This local variation in coupling configuration compensates for the varying capacitances at different plane positions, ensuring that each bit line experiences a uniform total capacitance across the entire array while maintaining versatile data access capability.
Solution Approach 2:
The coupling sequence parameter is varied across different memory blocks. By changing the order in which bit lines are coupled to plane positions in different blocks, the patent balances the total capacitance experienced by each bit line, transforming the non-uniform capacitance distribution into a uniform effective capacitance across all bit lines.
Data Source
AI summary
A 3D integrated circuit memory array has a plurality of plane positions. Multiple bit line structures have a multiple sequences of multiple plane positions. Each sequence characterizes an order in which a bit line structure couples the plane positions to bit lines. Each bit line is coupled to at least two different plane positions to access memory cells at two or more different plane positions.