Transistor TRIZ Cases

A manifolded gate resistance network distributes control voltage across series-connected transistors in radio-frequency switches.

Composite work function layers in FinFET gates resolve contradictions between high device density and performance reliability at nanometer nodes.

A three-dimensional memory device uses vertically oriented bit lines and laterally positioned transistors to increase integration density.

A color resin layer fills the step between the TFT structure and data line to enable horizontal liquid crystal driving.

A reflected-light receiving component captures stray laser light between the shield plate and optical module.

Inverted irradiation uses structure bodies as masks to pattern photoresist, eliminating expensive two-sided alignment equipment.

Gate structures serve as alignment references for dopant introduction, eliminating specialized masks and reducing process complexity.

A single masking process defines the upper electrode and silicide block layer simultaneously.

Ion-implanted doped layers prevent metal diffusion into silicon substrates, reducing parasitic losses in GaN devices.

Segmenting the body contact with a superlattice blocks dopant diffusion while reducing Schottky barrier height and contact resistance.

Shifting bit line coupling sequences across planes averages capacitance differences, stabilizing sensing margins and reducing manufacturing costs.

An oxide semiconductor transistor incorporates an insulating film with an excess oxygen region to reduce oxygen vacancies and stabilize threshold voltage.

A MOSFET metal gate stack uses a capping layer to create controlled footing structures that improve work function uniformity.

A dual-material mandrel patterns crystalline silicon to enable direct semiconductor deposition on fin sidewalls.

Selective epitaxial growth creates raised source and strap regions that maintain stable electrical resistance despite limited substrate thickness.

GaN epitaxial stack fabrication uses inert gas cooling to protect cap layers during deposition cooldown.

Nitrogen doping fills oxygen vacancies in the IGZO semiconductor lattice, improving transistor reliability without increasing manufacturing complexity.

A recessed FOX structure creates a U-shaped drift region in a MOSFET device to optimize charge density and cell pitch.

Stacking n-FET and p-FET nanosheets with rare earth oxide insulation reduces device footprint and leakage current beyond the 10 nm node.

Segmenting fin and isolation layer recess depths enables precise epitaxial stressor growth, enhancing carrier mobility while reducing source-drain resistance.

Quantum structures in ambipolar synaptic devices trap both electrons and holes, resolving the contradiction between retention time and operation voltage.

Segmented gate electrodes reduce area by over 60% while maintaining high resistance levels in CMOS bandgap reference circuits.

Heavily doped pockets at the source-channel junction minimize depletion barriers, boosting on-state current beyond 50 μA/μm for TFET logic applications.

A metal silicide e-fuse design reduces programming currents by sharing materials with resistor bodies.

A semiconductor structure merges two asymmetric MOS transistors to form a symmetric device using shared gate electrodes and specific source-drain connections.

A load switch circuit uses a comparison stage to activate specific adjustment modules for managing gate voltage.

Epitaxial fin extensions grow from etched fins with uniform crystal orientation, reducing parasitic capacitance by preventing uncontrolled merging.

Merging electrostatic discharge and test circuits via a shared signal line reduces parasitic capacitance, enabling narrow frame display panels.

Separate collector implants and dielectric spacers enable SiGe HBT and SOI CMOS co-fabrication, reducing parasitic RF losses.

Deep trench isolation structures lined with doped material reduce substrate leakage current by 100x and improve linearity without expensive SOI wafers.

A sandwiched oxide semiconductor structure achieves positive threshold voltage while reducing leakage current and enhancing field-effect mobility.

A segmented RC control circuit induces base current in N-level FET stacks, triggering cascaded parasitic conduction to prevent latch-up errors.

A thin film transistor structure uses a second insulating film to protect the oxide semiconductor channel layer during electrode formation.

A current source uses a nonvolatile storage element as a field-effect transistor to output stable bias.

Non-oxidized silicon layers prevent bowing and twisting in high aspect ratio openings, ensuring stable capacitor orientation during fabrication.

Segmented node contacts with internal voids lower parasitic capacitance, preventing data retention degradation while widening the fabrication process window.

A barrier pattern between an active region and a storage node contact increases process margin while reducing contact resistance.

Oxide semiconductor thin film transistor substrate design with transparent conductive electrodes.

Vertical stacking of silicon and dielectric levels increases memory cell density while maintaining a compact device footprint.

A switching regulator uses a charge pump to generate control signals for low start-up voltage operation.

Distinct oxide semiconductor compositions address manufacturing difficulty from varying acid resistance while ensuring mobility and light sensitivity.

Increasing the width of sidewall insulating films in memory transistors improves programming speed by enhancing resistance variation during charge accumulation.

Ion-implanted lateral etch barriers prevent isotropic undercutting from causing electrical shorts between the gate electrode and source/drain regions.

Selective removal of epitaxial spacer material establishes variable lateral gaps to enhance on-state currents without adding photolithographic steps.

Varying the doping concentration creates a threshold gradient that shunts leakage currents and prevents avalanche breakdown in hybrid circuits.

Oriented super junction structures in peripheral drift regions maintain high breakdown voltage while reducing on-resistance.

Segmenting switching units with mixed FET body types resolves the trade-off between insertion loss and harmonic distortion in RF circuits.

Integrating driver circuits on the display substrate using oxide semiconductor transistors reduces manufacturing costs while maintaining high on-state current.

Vertically stacked nanosheet transistors use suspended silicon germanium channels to enable electrostatic control.

Vertical transistors with buried bit lines and insulating grooves reduce impurity diffusion between adjacent pillars, overcoming short channel effects.