RC-Stacked MOSFET Circuit for High Voltage ESD Protection
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Solution Overview
Problem
High voltage integrated circuits are prone to latch-up errors due to electrostatic discharge (ESD) as the FET operating voltages exceed the design window, and stacked FET cell structures fail to trigger ESD protection before device breakdown, leading to potential damage.
Innovation Solution
A device with N-level stacks of field effect transistors (FETs) and an RC control circuit that causes a short circuit between pads in response to ESD events, triggering parasitic conduction in a cascaded manner to provide effective ESD protection by maintaining FET operating voltages within the design window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stacked FET cell structures are used to increase holding voltage, then the total holding voltage increases by a factor of N, but the trigger voltage also increases by a factor of N making it higher than BVDSS which prevents ESD protection from being triggered
Solution Approach 1:
The patent divides the stacked FET structure into N individual FET cells, each with its own RC control circuit. This segmentation allows each cell to be independently controlled and triggered at appropriate voltage levels, preventing the cumulative trigger voltage problem while maintaining the high holding voltage capability of the stacked configuration.
Solution Approach 2:
The patent introduces RC control circuits as intermediary elements between the ESD event and the FET cells. These RC circuits control the triggering of each FET cell individually, ensuring that they turn on at the appropriate voltage levels rather than requiring the entire stack to reach a prohibitively high trigger voltage.
2Strength
If FET operating voltages exceed the design window, then higher voltage handling is achieved, but latch-up errors occur and ESD protection fails
Solution Approach 1:
The patent implements preliminary action by using RC control circuits to proactively control the triggering of each FET cell before the operating voltage exceeds the design window. This preliminary control prevents latch-up errors by ensuring FETs are triggered at appropriate voltage levels rather than allowing voltages to exceed safe operating limits.
Solution Approach 2:
The patent employs feedback mechanisms through the RC control circuits that monitor voltage levels and control the triggering of FET cells accordingly. This feedback ensures that FETs are activated at the appropriate moment to protect against ESD while preventing latch-up conditions that would occur with uncontrolled voltage excursions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively protects high voltage integrated circuits from ESD by ensuring the FETs operate within their design window, preventing latch-up errors and ensuring reliable ESD protection without triggering before device breakdown.
Implementation Method 1
The ESD event causes the RC control circuit to induce a base current in each of the N ones of the FET, thereby triggering parasitic conduction of the N ones of the FET in a cascaded manner.
Implementation Method 2
An occurrence of an electrostatic discharge (ESD) can severely and irreparably damage unprotected electronic circuits, including HV integrated circuits.
Data Source
AI summary
Devices and methods of forming an integrated circuit (IC) that offer protection against ESD in high voltage (HV) circuit applications are disclosed. A device includes N ones of a field effect transistor (FET) stacked in series to provide an N-level stack, where N is an integer greater than 1. A first pad of the device is coupled to a first FET and a second pad is coupled to an Nth FET. The device also includes a stacked/distributed RC control circuit configured to cause a short circuit between the first pad and the second pad in response to an ESD event. During the ESD event, the RC control circuit is configured to concurrently provide sufficient voltage to control the N ones of the FET by turning them on using parasitic conduction to cause the short circuit.