Nanowire Semiconductor Device With Lateral-Etch Barrier
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Solution Overview
Problem
Conventional undercutting processes for forming suspended nanowires in nanowire field effect transistors (FETs) often lead to lateral etching, causing electrical short circuits between the gate electrode and raised source/drain regions due to the isotropic nature of the etching process.
Innovation Solution
The use of a semiconductor-on-insulator (SOI) wafer with etch barrier regions formed by implanting nitrogen or carbon ions into the buried insulator layer, creating a doped-oxide lateral-etch barrier layer that prevents lateral etching beneath the source/drain regions, allowing for controlled undercutting of the channel portion to form suspended nanowires while maintaining electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional isotropic etching process is used to undercut fins and form suspended nanowires, then complete surface access is achieved enabling gate-all-around configuration, but lateral etching occurs causing electrical short circuits between gate electrode and source/drain regions
Solution Approach 1:
The patent applies local quality by creating laterally-selective etching barriers in specific regions of the buried insulator layer. The etching barrier is formed only in regions laterally adjacent to source/drain regions, allowing isotropic etching to proceed in the gate region while preventing lateral etching beneath source/drain regions. This spatially differentiated etching resistance enables complete surface access for gate formation without causing electrical short circuits.
Solution Approach 2:
The patent introduces an intermediary etching barrier layer formed from the buried insulator layer material that is doped or modified to resist lateral etching. This intermediary structure mediates between the isotropic etching process and the source/drain regions, allowing the etch to undercut the fins in the gate region while blocking lateral propagation beneath the source/drain regions, thus preventing electrical shorts.
2Manufacturing precision
If isotropic etching is performed to undercut fins, then suspended nanowire structure is formed improving channel electrostatics control, but gate region laterally extends causing potential short circuits
Solution Approach 1:
The patent applies local quality by creating laterally-selective etching barriers in specific regions of the buried insulator layer. The etching barrier is formed only in regions laterally adjacent to source/drain regions, allowing isotropic etching to proceed in the gate region while preventing lateral etching beneath source/drain regions. This spatially differentiated etching resistance enables complete surface access for gate formation without causing electrical short circuits.
Solution Approach 2:
The patent applies preliminary action by pre-forming the etching barrier in the buried insulator layer before performing the isotropic etching process to undercut the fins. This pre-established barrier prevents unwanted lateral etching propagation during the undercutting process, ensuring that the suspended nanowire structure forms with precise lateral boundaries and preventing gate region extension that could cause shorts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents device shorting by ensuring that the etching process only undercuts the channel portion and not the source/drain regions, allowing for the formation of a gate-all-around configuration without electrical shorts, thereby improving the fabrication of nanowire FET devices.
Implementation Method 1
forming a semiconductor-on-insulator (SOI) wafer with etch barrier regions formed by implanting nitrogen or carbon ions into the buried insulator layer
Data Source
AI summary
A semiconductor device includes a semiconductor-on-insulator wafer having a buried layer. The buried layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel portion interposed between opposing source/drain portions. The channel portion is suspended in the gate region. A gate electrode is formed in the gate region, and completely surrounds all surfaces of the suspended nanowire. The buried layer comprises a first electrical insulating material, and the etch barrier regions comprising a second electrical insulating material different from the first electrical insulating material.