Segmented Node Contacts with Voids for Parasitic Capacitance Reduction
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to increased parasitic capacitance between node contacts in memory devices, degrading data retention properties and causing malfunctioning due to the need for taller node contacts and closer proximity, which complicates fabrication and affects electrical conduction.
Innovation Solution
A memory device is fabricated with node contacts containing voids and cutouts that are electrically isolated by insulating layers, reducing parasitic capacitance and allowing for relaxed fabrication requirements, while maintaining effective electrical conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If node contacts are made taller to compensate for reduced cross-sectional area, then capacitance is maintained, but fabrication difficulty increases and parasitic capacitance between adjacent contacts increases
Solution Approach 1:
The node contact structure is segmented into multiple portions with varying cross-sectional areas. The upper portion has a larger cross-sectional area than the lower portion, allowing the contact to maintain sufficient capacitance without requiring excessive height. This segmentation resolves the contradiction by distributing the capacitance function across different spatial regions rather than relying solely on increased height.
Solution Approach 2:
The invention transitions from a uniform cylindrical contact geometry to a multi-port ion structure with varying cross-sectional areas along the vertical dimension. By introducing dimensional variation in the contact structure, the patent achieves both sufficient capacitance and reduced fabrication difficulty, as the upper wider portion is easier to form and connect while the lower narrower portion maintains adequate spacing to reduce parasitic capacitance.
2Reliability
If node contacts are made taller to compensate for reduced cross-sectional area, then capacitance is maintained, but parasitic capacitance between adjacent contacts increases
Solution Approach 1:
The segmented structure with varying cross-sectional areas allows adjacent contacts to be positioned closer together horizontally while maintaining sufficient vertical separation through the tapered geometry. The upper wider portions can be spaced to reduce parasitic capacitance while the overall contact height maintains capacitance, resolving the contradiction between capacitance maintenance and parasitic capacitance reduction.
Solution Approach 2:
Different portions of the node contact have different cross-sectional areas optimized for different functions: the upper portion has larger area for ease of connection and reduced parasitic capacitance, while the lower portion has smaller area for maintaining capacitance with reduced height. This local quality variation resolves the contradiction by optimizing each region for its specific function.
3Area of stationary object
If miniaturization is pursued to increase device density, then device size is reduced, but parasitic capacitance between adjacent node contacts increases
Solution Approach 1:
The segmented node contact structure with varying cross-sectional areas enables closer horizontal spacing of adjacent contacts while maintaining adequate electrical isolation. The upper wider portions can be positioned to minimize parasitic capacitance coupling, while the overall compact vertical structure maintains small device footprint, resolving the contradiction between miniaturization and parasitic capacitance reduction.
Solution Approach 2:
By utilizing vertical dimensional variation in the contact structure rather than relying solely on horizontal spacing, the patent achieves both miniaturization and reduced parasitic capacitance. The tapered geometry allows compact horizontal layout while the vertical profile provides natural electrical isolation between adjacent contacts.
Data Source
AI summary
A memory device and a method of fabricating the memory device are disclosed, in which a plurality of contacts are formed on a substrate, and voids are formed in the contacts. The contacts are electrically isolated from one another by cutouts directly connecting with the voids. Insulating layers at least fill the cutouts. Since the cutouts are connected with the voids and the insulating layers fill at least the cutouts, the voids can be kept at least partially void. Thus, they can reduce parasitic capacitance between the contacts, prevent the degradation of data retention properties of the memory device, and overcome the problem of malfunctioning. Additionally, the need to avoid the formation of voids in the contacts by imposing strict requirements on the process for forming the contacts can be dispensed with, thus widening the process window for the formation of the contacts.