Ambipolar Synaptic Devices Using Quantum Traps for Low-Voltage Neuromorphic Computing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current synaptic devices based on charge trapping technologies, such as flash memory, require high voltage and current for operation, making them unsuitable for low-power applications like neuromorphic computing due to the energy needed for electron trapping and retention.
Innovation Solution
The development of ambipolar synaptic devices that include a semiconductor layer with a gate structure capable of injecting and trapping both electrons and holes, utilizing quantum structures as ambipolar traps to facilitate low-voltage operation and high drive currents, allowing for efficient synaptic function with reduced energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge trapping technology (flash memory architecture) is used to implement synaptic devices, then electron storage capability is achieved, but high voltage and current are required for operation
Solution Approach 1:
The patent changes the fundamental trapping mechanism from electron-only trapping in flash memory to ambipolar trapping that handles both electrons and holes. This parameter change in carrier type enables the device to operate at lower voltages and currents while maintaining reliable charge storage capability, directly resolving the contradiction between storage reliability and energy consumption
Solution Approach 2:
The ambipolar synaptic device achieves multi-functionality by incorporating structures that can trap both electrons and holes, unlike conventional flash memory that only traps electrons. This universal trapping capability allows the device to perform synaptic functions with bidirectional weight adjustment, achieving reliable storage while reducing operational energy requirements through more efficient charge manipulation
2Duration of action of stationary object
If high voltage is applied to trap electrons in floating gate, then sufficient retention time is achieved, but energy consumption increases
Solution Approach 1:
The patent changes the trapping parameter from unipolar electron trapping to ambipolar trapping of both electrons and holes. This enables the device to achieve sufficient retention time through more efficient charge storage mechanisms that do not require high voltage application, thereby reducing the energy consumed during trapping operations while maintaining data retention
Solution Approach 2:
The patent converts the previously harmful effect of requiring high voltage for trapping into a beneficial feature by implementing ambipolar trapping. The dual-carrier trapping mechanism allows the device to achieve both long retention time and low energy consumption, as the trapping process becomes more efficient and less energy-intensive while maintaining sufficient charge storage for retention
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These devices provide a small potential barrier for trapping, enabling low-operation voltages and high drive currents, making them suitable for neuromorphic computing applications while reducing power consumption.
Implementation Method 1
growing a channel layer containing quantum structures in the space such that the quantum structures are functional as ambipolar traps
Implementation Method 2
forming a source/drain structure including p+ and n+ regions adjoining the channel layer and configured to inject both electrons and holes into the channel layer
Data Source
AI summary
Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.