Raised Strap eDRAM on Thin SOI via Selective Epitaxy
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Solution Overview
Problem
The extremely thin semiconductor-on-insulator (ETSOI) substrate presents a challenge for reliable manufacturing of buried straps in eDRAM cells due to its limited thickness, which affects the vertical range of contact between the buried strap and the access transistor, leading to variations in electrical resistance and performance issues.
Innovation Solution
A deep trench is formed in the SOI substrate with a conductive trench fill region recessed to a depth coplanar with the top semiconductor layer, and a raised source and strap region are created using selective epitaxy to establish an electrically conductive path between the planar source region and the conductive fill region, avoiding the limitations of the shallow trench isolation structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a buried strap is formed underneath a shallow trench isolation structure in conventional eDRAM, then electrical connection between the deep trench capacitor and access transistor source is achieved, but in ETSOI substrates the limited thickness prevents reliable manufacturing and causes significant resistance variations
Solution Approach 1:
The patent transitions from a conventional planar buried strap configuration to a three-dimensional raised strap structure that extends vertically above the substrate surface. This dimensional change allows the strap to achieve sufficient contact length with the access transistor source region despite the limited ETSOI thickness, thereby maintaining reliable electrical connection while overcoming the thickness constraint.
Solution Approach 2:
The raised strap structure is formed through selective epitaxial growth on exposed semiconductor surfaces before final trench filling. This preliminary formation of the raised strap ensures proper positioning and electrical connection geometry is established early in the process, preventing resistance variations that would occur with post-processing adjustments.
2Ease of manufacture
If moderate variations in recess depth occur in conventional buried strap structures, then manufacturing flexibility is maintained, but significant variations in electrical resistance between source and deep trench inner node occur
Solution Approach 1:
The selective epitaxial growth process inherently provides self-regulating feedback mechanisms where the growth rate and termination are controlled by the exposure of specific crystal planes and mask patterns. This ensures that the raised strap achieves the correct dimensions and position regardless of minor variations in preceding process steps, thereby maintaining precise electrical resistance control while preserving manufacturing flexibility.
Solution Approach 2:
The patent utilizes changes in epitaxial growth parameters (temperature, pressure, gas flow, doping conditions) to precisely control the dimensions, doping concentration, and electrical properties of the raised strap. By adjusting these parameters, the electrical resistance can be optimized and maintained within tight specifications despite variations in recess depth or other manufacturing tolerances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures controlled and stable electrical resistance between the access transistor and the deep trench, enhancing the performance and reliability of eDRAM cells on ETSOI substrates by maintaining a compact size and high density.
Implementation Method 1
A selective epitaxy process is performed to deposit a raised source region and a raised strap region
Data Source
AI summary
A node dielectric and a conductive trench fill region filling a deep trench are recessed to a depth that is substantially coplanar with a top surface of a semiconductor-on-insulator (SOI) layer. A shallow trench isolation portion is formed on one side of an upper portion of the deep trench, while the other side of the upper portion of the deep trench provides an exposed surface of a semiconductor material of the conductive fill region. A selective epitaxy process is performed to deposit a raised source region and a raised strap region. The raised source region is formed directly on a planar source region within the SOI layer, and the raised strap region is formed directly on the conductive fill region. The raised strap region contacts the raised source region to provide an electrically conductive path between the planar source region and the conductive fill region.