Epitaxial Source/Drain Differential Spacers for Transistor Current Control
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Solution Overview
Problem
Achieving differential enhancement in on-state currents between transistors of the same polarity in integrated circuits using epitaxial source/drain layers without increasing fabrication cost and complexity has been challenging.
Innovation Solution
Forming transistors with a lateral space between the gate and source/drain epitaxial layers, where the first transistor has a greater space than the second transistor by at least 2 nanometers, by forming a conformal epitaxial spacer layer, anisotropically etching it on the first transistor, and removing it from the second transistor, thereby creating a performance differential without additional photolithographic operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial source/drain layers are used to enhance on-state currents in transistors, then transistor performance is improved, but achieving differential enhancement between different transistor types increases fabrication complexity
Solution Approach 1:
The patent applies local quality by forming epitaxial spacer layers selectively on different transistor gates with different thicknesses. First transistor gates receive a first thickness of epitaxial spacer material while second transistor gates receive a second thickness, creating locally differentiated structures that enable differential on-state current enhancement without requiring different fabrication processes for different transistor types
Solution Approach 2:
The patent utilizes parameter changes by varying the thickness parameter of the epitaxial spacer layer deposited on different transistor gates. By controlling the deposition time or rate to achieve different thicknesses on different gates, the patent creates performance differentiation through parameter variation rather than process differentiation
2Reliability
If additional photolithographic operations are added to achieve differential transistor performance, then performance differentiation is achieved, but fabrication cost and complexity increase
Solution Approach 1:
The patent applies universality by using a single photolithographic operation to define masks for both first and second transistor gates simultaneously. The epitaxial spacer deposition process serves multiple functions by creating different thicknesses on different gates in one step, eliminating the need for separate photolithographic steps for each transistor type
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for desired performance differences between transistors without increasing fabrication complexity or cost, enhancing on-state currents in integrated circuits.
Implementation Method 1
forming a conformal epitaxial spacer layer over the gates of the transistors
Implementation Method 2
anisotropically etching the epitaxial spacer layer on the first transistor gate so as to leave epitaxial spacers adjacent to the first gate
Data Source
AI summary
A process of forming an integrated circuit containing a first transistor and a second transistor of the same polarity, by forming an epitaxial spacer layer over gates of both transistors, performing an epitaxial spacer anisotropic etch process to form epitaxial spacers on vertical surfaces adjacent to the first transistor gate and removing the epitaxial spacer layer from the second transistor gate, subsequently performing a source/drain etch process and a source/drain epitaxial process to form source/drain epitaxial regions in the substrate adjacent to the first and second gates, such that the first source/drain epitaxial regions are separated from the first gate by a lateral space which is at least 2 nanometers larger than a second lateral space separating the second source/drain epitaxial regions from the second gate. An integrated circuit formed by the recited process.