Bandgap Reference Circuit Segmented Gate Design
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Solution Overview
Problem
CMOS reference circuits operating at low voltages and currents require high resistance, leading to large area requirements and inefficient manufacturing processes, as they need extensive masking steps and significant poly gate material, which is not suitable for modern applications demanding low power consumption and reduced device size.
Innovation Solution
An integrated circuit design with a bandgap reference circuit that includes a substrate with doped regions and a dielectric layer, reducing the area requirement by over 60% while maintaining resistance levels of 1 MΩ to 10 MΩ, achieved through optimized doping and spacing of doped regions and the use of a dielectric layer to minimize masking steps and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMOS transistors use high resistance to satisfy Ohm's law at low voltages and currents, then the resistance requirement is met, but the area requirement increases significantly
Solution Approach 1:
The gate electrode is segmented into multiple sections with different orientations (first gate electrode section with first orientation, second gate electrode section with second orientation). This segmentation allows achieving high resistance in a compact area by distributing the resistive function across multiple oriented sections rather than requiring a single large-area gate structure.
Solution Approach 2:
The patent introduces dimensional diversity by using gate electrode sections with different orientations (first orientation vs. second orientation). This multi-dimensional approach to gate electrode arrangement enables achieving the required resistance characteristics while reducing the overall planar area footprint of the transistor.
2Manufacturing precision
If extensive masking steps are used to form CMOS transistors with high resistance, then the resistance precision is improved, but the manufacturing complexity and time increase
Solution Approach 1:
Multiple gate electrode sections with different orientations are formed using a unified masking approach. The first gate electrode section and second gate electrode section are integrated into a single transistor structure through coordinated formation processes, reducing the need for separate extensive masking steps that would otherwise be required for each high-resistance element.
Solution Approach 2:
The gate electrode sections are formed with predetermined orientations and configurations during the initial transistor fabrication process. This preliminary structuring of the gate electrodes with different orientations enables subsequent resistance tuning without requiring additional complex masking steps, as the geometric configuration is already established.
3Reliability
If large area CMOS transistors are used to achieve high resistance, then the resistance level is satisfied, but the power consumption increases
Solution Approach 1:
The gate electrode is divided into multiple oriented sections that collectively provide the required resistance level. This segmentation allows achieving the target resistance with a smaller total gate area compared to a single large gate structure, thereby reducing the transistor area and associated power consumption while maintaining the necessary resistance characteristic.
4Reliability
If significant poly gate material is used to form high resistance CMOS transistors, then the resistance requirement is met, but the device size and manufacturing efficiency decrease
Solution Approach 1:
The patent employs gate electrode sections with different orientations (first orientation and second orientation) to achieve high resistance characteristics. This multi-dimensional gate configuration reduces the total amount of poly gate material required compared to conventional single-orientation gates, thereby decreasing device size and improving manufacturing efficiency through reduced material consumption and simpler processing.
Data Source
AI summary
A method of forming an integrated circuit comprises forming a first doped region and a second doped region in a substrate. The second doped region is formed separate from the first doped region by a first spacing. A dielectric layer is formed over the substrate, and a gate is formed over the dielectric layer. The gate is positioned having the first doped region on a first substrate side of the gate and the second doped region on a second substrate side of the gate, opposite the first substrate side of the gate. A third doped region is formed in the substrate separated from the first doped region by a second spacing. The method further comprises forming a fourth doped region in the substrate.