Array Substrate Circuit Shared Electrostatic Discharge Test Signal Line
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Solution Overview
Problem
High-end display panels face challenges with large parasitic capacitance loads due to numerous peripheral circuits, leading to signal delays and poor display performance, and a larger circuit area hinders the achievement of a narrow frame design.
Innovation Solution
An array substrate circuit design where the electrostatic discharge circuit and test circuit share a portion, reducing the overall circuit area and load by integrating their functions, allowing for a compact circuit structure that supports a narrow frame panel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate electrostatic discharge circuit and test circuit are designed, then circuit functionality is complete, but circuit area and parasitic capacitance load increase
Solution Approach 1:
The patent merges the electrostatic discharge circuit and test circuit by making the test signal line share the first signal line with the electrostatic discharge circuit. This integration reduces the overall circuit area while maintaining both electrostatic discharge protection and test functionality, directly resolving the contradiction between complete circuit functionality and minimized circuit area.
Solution Approach 2:
The first signal line serves dual purposes: it functions as an electrostatic discharge path during electrostatic events and as a test signal path during testing operations. This multi-functionality allows a single circuit element to fulfill multiple roles, reducing the total number of components and overall circuit area while ensuring both protection and testing capabilities remain intact.
2Manufacturing precision
If more peripheral circuits are added for high resolution, then display quality improves, but parasitic capacitance load increases causing signal delay
Solution Approach 1:
By merging the test circuit with the electrostatic discharge circuit through shared signal lines, the patent reduces the total number of peripheral circuits required. This consolidation minimizes the parasitic capacitance load that would otherwise accumulate from numerous separate circuits, thereby reducing signal delay while still enabling high-resolution display functionality.
3Reliability
If larger circuit area is used, then circuit functionality is complete, but narrow frame design becomes difficult
Solution Approach 1:
The patent combines the electrostatic discharge circuit and test circuit into a compact integrated structure using shared signal lines and common circuit elements. This merging dramatically reduces the spatial footprint of the peripheral circuits, enabling the display panel to achieve a narrow frame design while maintaining complete circuit functionality for both protection and testing operations.
Data Source
AI summary
An array substrate circuit including an electrostatic discharge circuit for supplying electrostatic discharge to a first signal line for supplying a test signal to the first signal line; wherein, the electrostatic discharge circuit and the test circuit have a shared portion. The array substrate circuit can achieve a lower load of a signal line, and is conducive to achieving a narrow frame panel. An array substrate including the array substrate circuit and a display device are further disclosed.