3D Memory Device With Embedded Word Lines
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited due to the high cost of miniaturization and the need for advanced equipment, prompting the exploration of three-dimensional memory devices with vertically arranged memory cells.
Innovation Solution
A three-dimensional memory device design featuring vertically oriented bit lines, laterally positioned transistors with embedded word lines, and capacitors, along with a lateral active layer and plate lines, enhancing integration density without the need for expensive miniaturization equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional planar semiconductor devices are miniaturized to increase integration degree, then the integration degree is improved, but the manufacturing cost increases and advanced equipment is required
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cells are stacked in the vertical direction (first direction) sharing common bit lines and plate lines, thereby increasing integration degree without requiring further miniaturization of individual cell dimensions. This dimensional transition eliminates the need for expensive advanced lithography equipment while achieving higher density.
2Quantity of substance
If two-dimensional planar semiconductor devices are miniaturized to increase integration degree, then the integration degree is improved, but the manufacturing precision requirements increase
Solution Approach 1:
By stacking memory cells vertically in the first direction, the patent achieves higher integration without requiring finer lateral pattern dimensions. The word lines extend in the second direction and penetrate through the vertically stacked structure, while bit lines and plate lines are arranged vertically, creating a three-dimensional architecture that reduces lateral patterning requirements and associated precision constraints.
3Quantity of substance
If three-dimensional memory cells are stacked vertically, then the degree of integration is increased, but the device complexity increases
Solution Approach 1:
Multiple memory cells are merged by sharing common bit lines and plate lines across the vertically stacked structure. The bit lines and plate lines extend in the vertical direction to serve multiple cell levels, reducing the total number of conductive interconnects required and simplifying the overall device structure despite the three-dimensional cell arrangement.
Solution Approach 2:
The vertically oriented bit lines and plate lines serve multiple functions by simultaneously connecting to multiple memory cells at different vertical levels. This multi-functional design allows a single conductive line to address and control multiple storage nodes across the stacked structure, reducing complexity compared to having separate interconnects for each cell.
Data Source
AI summary
A memory cell includes: a bit line and a plate line that are spaced apart from each other and vertically oriented in a first direction; a transistor including an active layer, the active layer being laterally oriented in a second direction, intersecting with the bit line; a capacitor laterally oriented in the second direction between the active layer and the plate line; and a word line laterally oriented in a third direction, intersecting with the bit line and the active layer, wherein the word line is embedded in the active layer.