Vertical Transistor Buried Bit Line Isolation
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Solution Overview
Problem
The miniaturization of transistors in semiconductor devices has reached its limit, leading to short channel effects that hinder accurate operation, and existing methods for addressing this issue, such as three-dimensionally forming transistors, face challenges in achieving efficient integration and reducing impurity diffusion between adjacent transistors.
Innovation Solution
The semiconductor device incorporates a structure with vertical transistors featuring grooves and buried bit lines that extend under pillars, with impurity diffusion layers forming as source or drain, and a double gate structure, allowing for a close-packed layout and reduced impurity diffusion between adjacent transistors, thereby enhancing integration and operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are miniaturized to improve integration, then the degree of integration increases, but short channel effects occur that hinder accurate operation
Solution Approach 1:
The patent transitions from planar transistors to vertical transistors by extending the channel in the vertical dimension. The silicon pillar extends vertically from the semiconductor substrate surface, creating a three-dimensional structure where the channel length is defined by the vertical depth rather than horizontal spacing. This dimensional change allows for smaller horizontal footprints while maintaining adequate channel lengths to avoid short channel effects.
2Reliability
If vertical transistors are formed to overcome miniaturization limits, then transistor performance improves, but impurity diffusion between adjacent transistors increases
Solution Approach 1:
The patent extracts and removes semiconductor material to form trenches between adjacent vertical transistor pillars. These trenches are then filled with insulating material to create isolation regions. By removing the problematic semiconductor material that would otherwise allow impurity diffusion and filling with insulator, the harmful impurity diffusion pathway is eliminated while preserving the vertical transistor structure.
Solution Approach 2:
The patent introduces insulating material as an intermediary substance between adjacent vertical transistors. This insulating layer acts as a barrier that prevents impurity diffusion between neighboring transistor regions while allowing each transistor to maintain its vertical structure and electrical characteristics independently.
3Ease of manufacture
If bit lines are disposed below silicon pillars, then capacitor placement is optimized, but manufacturing complexity increases due to buried bit line requirements
Solution Approach 1:
The patent forms the buried bit lines at an early stage in the manufacturing process, before the vertical transistor pillars are fully formed. By preparing the bit line structures in advance and embedding them in the semiconductor substrate, subsequent processing steps can focus on forming the vertical pillars and capacitors without needing to navigate around complex existing structures, thereby managing overall manufacturing complexity.
Data Source
AI summary
A semiconductor device includes an isolation region, a semiconductor region, a groove, and an insulating film. The semiconductor region is defined by the isolation region. The groove is in the semiconductor region. The groove has first and second ends. At least one of the first and second ends reaches the isolation region. The insulating film is in the groove.