Vertically Stacked Nanosheet CMOS Transistor Architecture
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Solution Overview
Problem
Conventional nanosheet-based CMOS structures face challenges in scaling beyond the 10 nm node due to difficulties in fabricating high-density transistor architectures, particularly in managing device footprint and leakage current, as traditional methods require a large device footprint for arranging n-FET and p-FET side by side.
Innovation Solution
The proposed solution involves a vertically stacked nanosheet CMOS transistor architecture where p-FET and n-FET are stacked on top of each other, utilizing epitaxially grown rare earth oxides to insulate and isolate the nanosheets, reducing source/drain leakage current and improving epitaxial growth quality, thereby minimizing device footprint and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If n-FET and p-FET are arranged side by side in conventional nanosheet-based CMOS structures, then the device can function properly, but the device footprint becomes large, making scaling beyond the 10 nm node difficult
Solution Approach 1:
The patent transitions from a planar side-by-side arrangement of n-FET and p-FET to a vertical stacked configuration. By stacking the p-FET nanosheet stack above the n-FET nanosheet stack separated by an intermediate rare earth oxide layer, the device utilizes the vertical dimension to achieve higher density while reducing the lateral footprint, enabling scaling beyond the 10 nm node
2Ease of manufacture
If traditional fabrication methods are used for nanosheet-based CMOS, then the process is simpler, but leakage current management becomes difficult and device performance deteriorates
Solution Approach 1:
The patent introduces an intermediate rare earth oxide layer between the n-FET and p-FET nanosheet stacks. This intermediate layer acts as a mediator that provides electrical isolation and reduces source/drain leakage current while maintaining fabrication compatibility with existing epitaxial growth processes, thus managing harmful leakage effects without significantly complicating manufacturing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces device footprint, improves source/drain leakage current management, and ensures better epitaxial growth quality, enabling the scaling of nanosheet-based CMOS structures beyond the 10 nm node by vertically stacking n-FET and p-FET, resulting in increased density and performance.
Implementation Method 1
utilizing epitaxially grown rare earth oxides to insulate and isolate the nanosheets
Implementation Method 2
A second rare earth oxide layer is formed on the first nanosheet stack... utilized to insulate and isolate the nanosheets
Data Source
AI summary
Embodiments of the present invention are directed to techniques for generating vertically stacked nanosheet CMOS (Complementary Metal Oxide Semiconductor) transistor architectures. In a non-limiting embodiment of the invention, a first rare earth oxide layer is formed over a substrate. An n-FET nanosheet stack is formed on the rare earth oxide layer. The n-FET nanosheet stack includes a first nanosheet. A second rare earth oxide layer is formed on the n-FET nanosheet stack. A p-FET nanosheet stack is formed on the second rare earth oxide layer. The p-FET nanosheet stack includes a second nanosheet.