3D Stacked Memory Cells for High Density Storage
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Solution Overview
Problem
The increasing demand for higher storage capacity in memory devices while maintaining a small device size poses a challenge in increasing memory cell density, as existing technologies struggle to efficiently pack more memory cells without compromising performance.
Innovation Solution
A three-dimensional stacked structure is used to form horizontal silicon strings within the substrate, allowing for increased memory density by stacking memory cells along multiple levels of semiconductor material separated by dielectric material, with control gates and charge storage structures between them, enabling efficient access and programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased to meet higher storage capacity demand, then storage capacity is improved, but device size control becomes more difficult
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangement to a three-dimensional stacked structure with multiple levels (first level, second level, third level) of semiconductor material. This vertical stacking enables memory cells to be arranged in three dimensions, significantly increasing storage capacity while maintaining a compact device footprint by utilizing the vertical dimension rather than expanding horizontally.
2Quantity of substance
If more memory cells are packed into the device, then storage capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The memory device is segmented into multiple distinct levels (first level, second level, third level) of semiconductor material, each separated by insulating material layers. This segmentation allows for modular fabrication processes where each level can be formed and processed relatively independently, reducing the overall manufacturing complexity compared to attempting to create a monolithic high-density structure.
Solution Approach 2:
By stacking memory cells vertically across multiple levels separated by insulating material, the patent achieves high memory cell density without proportionally increasing manufacturing complexity. The repetitive layered structure allows for scalable fabrication processes that can be extended to additional levels without fundamentally changing the manufacturing approach.
Data Source
AI summary
Various embodiments include methods and apparatuses including strings of memory cells formed along levels of semiconductor material. One such apparatus includes a stack comprised of a number of levels of single crystal silicon and a number of levels of dielectric material. Each of the levels of silicon is separated from an adjacent level of silicon by a level of the dielectric material. Strings of memory cells are formed along the levels of silicon. Additional apparatuses and methods are disclosed.