FinFET Stressor Layer Control via Recess Segmentation
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing fin field effect transistors (FinFETs) with high aspect ratio fins, where controlling the dimensions of the isolation insulating layer and fin recesses is crucial for achieving optimal carrier mobility and device performance, as existing methods struggle to accurately control the depth and volume of epitaxially grown stressor layers in the source/drain regions.
Innovation Solution
The method involves forming a fin structure over a substrate, creating a gate structure, and recessing the fin and isolation insulating layers such that the depth of the fin recess is set smaller than the depth of the isolation insulating layer recess, allowing for accurate control of the epitaxially grown stressor layer, which enhances carrier mobility and reduces gate and source/drain resistances by selectively growing strained materials like SiC and SiGe in the recessed portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the depth of fin recess is made equal to the depth of isolation insulating layer recess, then the manufacturing process is simpler, but the control precision of epitaxially grown stressor layer dimensions deteriorates
Solution Approach 1:
The patent segments the recess formation process into two distinct stages: first forming a recess in the isolation insulating layer, then forming a shallower recess in the fin structure. This segmentation allows independent optimization of each recess depth, enabling precise control over the stressor layer formation zone while maintaining manufacturing feasibility through standardized processing steps.
Solution Approach 2:
The patent performs preliminary action by first forming the deeper isolation insulating layer recess before forming the fin recess. This preliminary deeper recess provides a prepared substrate that guides subsequent epitaxial growth, ensuring the stressor layer forms with controlled dimensions and proper stress distribution before the actual device fabrication continues.
2Reliability
If strained materials are added to source/drain regions, then carrier mobility is enhanced, but the device complexity increases
Solution Approach 1:
The patent applies local quality by introducing strained materials specifically in the source and drain regions adjacent to the channel, while keeping the channel region itself unstrained. This localized strain application enhances carrier mobility where needed (at the interfaces) without complicating the overall device structure or requiring strained channel materials, thus improving performance with minimal added complexity.
Solution Approach 2:
The patent utilizes composite material structures by combining strained semiconductor materials (such as SiGe or SiC) with standard silicon in the source/drain regions. This composite approach allows the device to benefit from the high carrier mobility of strained materials at critical interfaces while maintaining the electrical and manufacturing advantages of standard silicon in the channel, achieving performance enhancement without excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance by accurately controlling the stressor layer dimensions, leading to increased carrier mobility, reduced resistances, and enhanced reliability of FinFETs, thereby addressing the limitations of existing manufacturing processes.
Implementation Method 1
allowing for accurate control of the epitaxially grown stressor layer, which enhances carrier mobility and reduces gate and source/drain resistances by selectively growing strained materials like SiC and SiGe in the recessed portions
Data Source
AI summary
A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.