3D Memory Bit Line Voltage Adjustment for Partial Erase Read Failures
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Solution Overview
Problem
3D memory devices face challenges in maintaining reliable read operations due to variations in threshold voltages caused by partial erase operations, leading to potential read failures, especially when partial erase operations are performed on sub-memory blocks at different positions within the memory block.
Innovation Solution
The solution involves a method for operating a 3D memory device where the bit line voltage is adjusted based on the presence and position of partially erased sub-memory blocks during a read operation. If a partially erased sub-memory block is present, the bit line voltage is varied depending on the position of the target sub-memory block, and the number of partially erased sub-memory blocks, to prevent read failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a partial erase operation is performed on sub-memory blocks, then storage flexibility and program efficiency are improved, but threshold voltage variations occur leading to read failures
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the bit line voltage level based on the presence and position of partially erased sub-memory blocks. When a partial erase operation is detected, the system changes the voltage parameter to compensate for threshold voltage variations, thereby maintaining read operation reliability while preserving the productivity benefits of partial erase operations.
Solution Approach 2:
The patent implements local quality by applying different bit line voltage levels to different sub-memory blocks based on their erase status. Specifically, sub-memory blocks that have undergone partial erase operations receive different voltage treatment compared to fully programmed blocks, allowing the system to address threshold voltage variations locally rather than applying a uniform approach to the entire memory block.
2Reliability
If bit line voltage is adjusted based on sub-memory block position, then read failure rate is reduced, but control complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory block into multiple sub-memory blocks and tracking their individual erase statuses. The control logic processes each sub-memory block separately, determining whether it has undergone partial erase and applying appropriate voltage levels accordingly. This segmented approach manages complexity by breaking down the control task into smaller, more manageable units.
Solution Approach 2:
The patent implements preliminary action by pre-determining the bit line voltage level based on the erase status of sub-memory blocks before the actual read operation commences. The control logic identifies which sub-memory blocks require voltage adjustment and prepares the appropriate voltage levels in advance, ensuring that the correct voltage is applied without adding complexity during the read operation itself.
Data Source
AI summary
A memory device includes a memory block including a plurality of stacked sub-memory blocks, peripheral circuits configured to perform program, read and erase operations on the memory block or on a block selected from among the sub-memory blocks, and a control logic configured to control the peripheral circuits so that, during a read operation on the memory block, if a block on which a partial erase operation has been performed is not present among the sub-memory blocks, voltages to be used for the read operation are set and so that, if a block on which the partial erase operation has been performed is present among the sub-memory blocks, the voltages to be used for the read operation are varied depending on a position of a sub-memory block that is a target of the read operation.