Read-Only Memories TRIZ Cases

Using control gates with word lines in flash VMM arrays improves in-memory computing accuracy and speeds weight programming through rerouted erase lines.

Adding carbon, boron, phosphorus, or metal to silicon nitride creates deeper traps that improve charge retention in NAND memory cells.

Asymmetric floating-gate shapes and selective gate spacing equalize coupling ratios, improving threshold voltage uniformity and read reliability.

Columnar memory strings are formed without wet etching, protecting gate insulation layers while lowering contact resistance and supporting denser 3D storage.

A stacked semiconductor and conductive layer structure boosts NOR flash density and capacity while supporting efficient write, read, and erase operations.

Shared active regions and conductive lines cut parasitic resistance, enabling accurate fuse status testing in compact semiconductor layouts.

A serially coupled flash and embedded NVM cell enables single-read multi-state access while avoiding the cost and power penalty of pure embedded memory.

Self-aligned sidewalls and sacrificial lines improve electrical access and lateral alignment in vertically stacked NAND memory arrays.

Strategic indium implants reshape electric fields in a floating-gate NOR memory cell to speed programming while preserving read current.

Precharge and clock-doubling keep the final flash memory charge pump stage conductive, avoiding voltage droop at low VDD.

Protruding insulating layers over adjacent gate electrodes shrink element isolation width while preserving processing margin and transistor density.

A concave drain extension under shallow trench isolation improves FET isolation and helps prevent gate dielectric breakdown at high erase voltages.

A dual-level charge-trap stack improves synaptic weight linearity and update speed while preserving nonvolatile retention and CMOS compatibility.

An inclined 2D charge trap layer limits lateral charge spreading, helping nonvolatile memory cells raise storage density without data errors.

Gate connection structures and dummy supports keep 3D memory gate stacks stable during etching while maintaining reliable electrical links.

An added dopant path and cascaded select transistors raise OTP read current and margin while easing programming voltage stress.

A wrapped floating gate with vertical protrusions increases channel interface area to improve charge injection, programming efficiency, and read window.

A segmented resonant tunneling barrier and high-mobility vertical channel improve charge retention, lower programming voltage, and raise 3D memory density.

A buried dummy structure and self-aligned etching shrink active-to-protrusion spacing while preserving threshold voltage and process uniformity.

Alternating oxide and nitride sidewall spacers block leakage paths in MTP memory cells, preserving data retention over repeated write cycles.

A buffer region between stacked NAND decks prevents material shaving and opening misalignment, improving memory cell formation accuracy.

A switch isolates the capacitor from the detection circuit during initial boosting to prevent ripple-driven malfunction and speed voltage rise.

In-situ heating anneals floating-gate memory defects, releasing trapped carriers to extend flash endurance under frequent writes.

A continuous line-and-via structure forms stairless 3D memory word line contacts through dielectric layers without material junctions.

Preformed alignment marks and sacrificial trenches help 3D NAND arrays achieve precise string coupling, improving retention time and access.

Vertical stacking and GAA channel formation increase memory cell density while controlling interconnect complexity and power use.

Sharp-corner anti-fuse gate geometry creates multiple oxide breakdown points, improving DRAM programming consistency and yield.

A conductive discharge path between the source line and substrate suppresses arcing during high aspect ratio etching and improves yield.

Different-work-function gates and voltage control suppress word-line coupling noise in single-transistor DRAM while improving data hold and read accuracy.

Fuse-switched resistor paths let an analog divider set a reference voltage within limits, then lock it against later changes for safety approval.

Vertical floating-gate protrusions expand channel interface area to ease charge injection in scaled flash memory and improve programming and read window.

Shared segmented gates and trench isolation pack different-voltage FETs more densely while preserving voltage-specific operation in memory circuits.

Offset memory cells across shared bit lines and split word lines above and below the array to cut disturb without losing 3D NOR density.

Selective fill and isotropic etch create variable-thickness gate lines in 3D memory stacks, lowering resistance without widening cell spacing.

Matched reference-current cells mirror memory-cell drift, enabling more accurate current sensing and long-term neural network data reads.

High-mobility 2D semiconductor channels help vertical NAND sustain cell current and program speed as stack height increases.

Mixed ferroelectric and antiferroelectric HZO layers preserve polarization and memory window stability across repeated memory cycles.

Submicron vias and separated high- and low-temperature layers raise 3D memory connectivity without damaging underlying metal interconnects.

A doped floating liner in transistor isolation trenches raises breakdown voltage while enabling narrower, shallower trenches and better voltage modulation.

A sidewall native oxide layer shields 3D NAND blocking layers during gate replacement, reducing etchant damage and preserving memory reliability.

Segmented gate control and impact ionization reduce word-line coupling noise, preserving logic-state separation in capacitorless DRAM cells.

Dynamic charge pump capacity switching uses low-voltage detection and feedback to curb output ripple and peripheral circuit stress.

Read voltages are tuned by program-state usage frequency to improve memory-cell access, weight precision, and neural-network efficiency.

A barrier pattern beside the penetration contact protects connection insulating patterns, improving 3D memory yield and electrical reliability.

A thick gate layer and impurity-diffused source region improve channel induction and electrical erase in stacked 3D nonvolatile memory cells.

Switchable series and parallel charge pump stages generate read, program, and test voltages in one memory IC while reducing area.

Adjustable resistance isolates a secondary memory chip during shared-node reads, cutting noise and preserving signal quality and data integrity.

A continuous shared channel and segmented gates simplify split-gate flash cells while improving voltage coupling, bit-selective programming, and erase.

A stacked 3D memory layout alternates sub-bit and sub-source lines between cell columns to raise density while limiting interconnect complexity.

Shared global and local regulators with cascode switching cut memory-plane power and area while sustaining independent wordline read performance.

A bridge chip duplicates and synchronizes command sequences across channels to cut memory transfer processing time between chips.

Vertical memory stacking with bonded metal pads cuts noise coupling, simplifies fabrication, and speeds bias charging in 3D nonvolatile memory.

A two-stage eye diagram search calibrates flash interface voltage and timing offsets to enable faster NAND data transfer without signal errors.

A barrier metal film and covering layer protect memory conductors from damage and water ingress while preserving electrical integrity.

Adjusting row and column switch turn-on levels controls write current, enabling multi-level memory storage without process changes.

A plate line parallel to each word line erases floating-body carriers, enabling stable write and refresh without bit-line disturb.

Parallel refresh and program verification through switched sense amplifiers cuts flash memory verification time during erase operations.

Different decode timing and voltage settings for open and closed memory blocks cut Icc spikes during parallel non-volatile memory reads.

Transfer voltage is varied by bits written to equalize program disturbance and improve data retention in stacked semiconductor memory.

Subset-based enable logic lets multiple memory units be tested in parallel, cutting ATPG time and semiconductor area without added power-grid complexity.

A shared current path lets eFuse memory cells handle programming and reading with fewer components, reducing unit cell and chip area.

Foggy and fine program pass loop control cuts memory-cell interference, verification time, and power during programming.

Shared comparators and logic calibrate pull-up and pull-down drivers for DDR3 and LPDDR4 NAND Flash with less silicon area.

A master DRAM chip shares reference voltages with slave chips, cutting DC current use while preserving signal determination capability.

Temporarily lowering bitline voltage during wordline settling cuts read power and restores stable sensing in non-volatile memory.

A two-phase data-line charging scheme enables concurrent threshold verification while limiting capacitance-driven charge decay and verify time.

XOR-based RAIN parity across consecutive word lines helps NAND memory recover simultaneous read distress and program disturb errors.

An oxidized buffer layer and gettering process improve 3D memory channel crystallization uniformity while limiting metal catalyst-related reliability loss.

A single row clear command writes pre-stored data patterns across memory columns to cut bus occupancy, power use, and clear time.

Distinct terminal groups for single-ended and differential signals support SD and PCIe while reducing lane skew at higher transfer speeds.

Counts neighboring aggressor-cell states to set read-voltage offsets, reducing threshold distortion and flash data recovery errors.

Stacked gate lines and low-k gap-fill layers cut parasitic capacitance and RC delay in dense 3D semiconductor memory structures.

A split sensing node and separation transistor stabilize trip voltage, preserving NAND read margins and data accuracy at low voltage.

A lower pass voltage on the last unselected wordline cuts hot-electron injection and program disturb, improving edge data accuracy.

Page-level last written page tracking per die corrects scan misalignment and reduces media and read disturb scan errors.

Alternating paired channel strings across conductive and insulative tiers raise 3D NAND density while improving lateral cell isolation.

Boosted read-voltage modulation captures soft bits next to hard-bit reads, cutting retry latency and improving memory decoding.

Weight data is grouped by neural network layer and spread across memory channels to cut page reads, power use, and AI inference latency.

Isolation trenches act as lateral etch stops to control sacrificial removal, prevent stray conductors, and preserve memory die area.

Power-gate and cascode-gate transistors cut leakage and area in metal-fuse memory circuits while preserving programming and read accuracy.

Distributed ANN accelerators share input data and weights through a universal interconnect to cut GPGPU dependence, power use, and hardware cost.

Shared power rails and aligned sense timing let NAND planes read independently while cutting noise, die area, and read delays.

Pre-charging flash memory channels before wordline recovery reduces channel-wordline voltage gaps and stabilizes read and program reliability.

Different pass voltages on unselected word lines reduce potential differences, lowering program verification errors and power use.

Timed voltage changes on grouped ground selection lines cut pre-pulse recovery time and power during nonvolatile memory reads.

Adjusted selected and unselected word-line voltages add a pre-read step that tracks threshold shifts and improves memory-cell sensing accuracy.

Current-based signal cycling adapts anti-fuse writing to process variation, improving write consistency while avoiding excess energy.

Dynamic address scrambling changes memory mapping when attack conditions are detected, helping resist row hammering and protect data integrity.

Buried dummy structures formed by self-aligned patterning shrink active-dummy spacing while stabilizing threshold voltage and process variability.

A single program pulse with boosted and selectively discharged sub-block channels cuts NAND SLC programming latency while preserving completion.

Splitting pass transistors across two P-type substrate regions improves 3D NAND selection-line setup speed, chip area, and timing reliability.

Sacrificial staircase formation stabilizes tall vertical memory stacks and lowers parasitic capacitance to improve reliability and power use.

Separate memory blocks use smaller cells for normal data and larger cells with current compensation for critical data reliability.

Dynamic prologue selection cuts redundant first-stage parameter calculations in 3D NAND SLC programming, reducing write time.

Stacked memristor cell strings and layer selection enable parallel neural computation with high integration and lower power use.

Segmented source plates enable precise memory sub-block activation while reducing select-gate segregation, block width, and threshold variability.

Word line select transistors isolate local word lines in 3D NOR ferroelectric memory, cutting global line capacitance, latency, and disturb.

Independent command and data periods cut NAND interface overhead and let multiple memory dies run in parallel without overlapping I/O.

Parasitic coupling from an adjacent bit line raises precharge voltage to preserve sensing margin during low-voltage memory read operations.

An adaptive memory-state partitioning scheme configures end cells to store fewer bits than intermediate cells within a NAND string.

Segmenting flash memory program levels into distinct sets for hot and cold data increases programming cycle tolerance while reducing read latency.

Control means apply erase verify voltage to word lines during non-volatile memory erase operations.

Segmenting the erase operation with a preliminary pulse and edge biasing prevents electron tunneling degradation in NAND flash memory blocks.

Dynamic redundancy address latches enable universal testing of fuse and non-fuse repair structures, resolving development complexity trade-offs.

A three-dimensional nonvolatile memory device stacks drive circuits and memory cells in separate layers to reduce transistor size.

Under-array CMOS sensing with vertical bitline connections reduces memory area while managing process variability.

A memory controller tracks read counts and error thresholds to initiate data reclamation before uncorrectable errors occur.

Bit line select gates connect a single page buffer to multiple bit lines, increasing data read/write throughput without expanding die size.

An EEPROM refresh controller manages timing signals between the memory array and an external system to coordinate data retention operations.

Segmenting a DRAM die into self-refresh and controller-managed modes reduces power consumption while maintaining data integrity.