Read-Only Memories TRIZ Cases
- Flash VMM Arrays Using Control Gates for Accurate In-Memory Computing
Using control gates with word lines in flash VMM arrays improves in-memory computing accuracy and speeds weight programming through rerouted erase lines.
- Charge-Trapping Memory Cells with Additives for Better Retention
Adding carbon, boron, phosphorus, or metal to silicon nitride creates deeper traps that improve charge retention in NAND memory cells.
- Asymmetric Floating-Gate Layout for Uniform Memory Threshold Voltage
Asymmetric floating-gate shapes and selective gate spacing equalize coupling ratios, improving threshold voltage uniformity and read reliability.
- 3D NAND Memory String Structure Without Wet Etching Damage
Columnar memory strings are formed without wet etching, protecting gate insulation layers while lowering contact resistance and supporting denser 3D storage.
- 3D NOR Flash Memory Cell Structure for Higher Integration
A stacked semiconductor and conductive layer structure boosts NOR flash density and capacity while supporting efficient write, read, and erase operations.
- Fuse Element Array Layout for Accurate Blown Resistance Testing
Shared active regions and conductive lines cut parasitic resistance, enabling accurate fuse status testing in compact semiconductor layouts.
- Integrated Memory Cell Layout for Single-Read Multi-State Access
A serially coupled flash and embedded NVM cell enables single-read multi-state access while avoiding the cost and power penalty of pure embedded memory.
- Vertical Memory Array Structure for Self-Aligned Electrical Access
Self-aligned sidewalls and sacrificial lines improve electrical access and lateral alignment in vertically stacked NAND memory arrays.